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data sheet femtoclock ? ng universal frequency translator 8T49N241 8T49N241 revision 1 08/07/15 1 ?2015 integrated device technology, inc. general description the 8T49N241 has one fractional-f eedback pll that can be used as a jitter attenuator and frequency translator. it is equipped with one integer and three fractional output dividers, allowing the generation of up to four different output frequenc ies, ranging from 8khz to 1ghz. these frequencies are completely independent of each other, the input reference frequencies and the crystal reference frequency. the device places virtually no constrai nts on input to output frequency conversion, supporting all fec rates, including the new revision of itu-t recommendation g.709 (20 09), most with 0ppm conversion error. the outputs may select among lvpecl, lvds, hcsl or lvcmos output levels. this makes it ideal to be used in any frequency synthesis application, including 1g, 10g, 40g and 100g synchronous ethernet, otn, and sonet/sdh, including itu-t g.709 (2009) fec rates. the 8T49N241 accepts up to two differential or single-ended input clocks and a fundamental-mode crystal input. the internal pll can lock to either of the input referenc e clocks or just to the crystal to behave as a frequency synthesizer. the pll can use the second input for redundant backup of the primary input reference, but in this case, both input clock references must be related in frequency. the device supports hitless reference switching between input clocks. the device monitors both input clocks for loss of signal (los), and generates an alarm when an input clock failure is detected. automatic and manual hitless reference switching options are supported. los behavior can be set to support gapped or un-gapped clocks. the 8T49N241 supports holdover. the holdover has an initial accuracy of 50ppb from the point where the loss of all applicable input reference(s) has been detect ed. it maintains a historical average operating point for the pll that may be returned to in holdover at a limited phase slope. the pll has a register-selectable loop bandwidth from 0.2hz to 6.4khz. the device supports output enable & clock select inputs and lock, holdover & los status outputs. the device is programmable through an i 2 c interface. it also supports i 2 c master capability to allow the register configuration to be read from an external eeprom. programming with idt?s timing commander software is recommended for optimal device performance. factory pre-programmed devices are also available. applications ? otn or sonet / sdh equipment ? gigabit and terabit ip switches / routers including synchronous ethernet ? video broadcast features ? supports sdh/sonet and synchronous ethernet clocks including all fec rate conversions ? 0.35ps rms typical jitter (including spurs): 12khz to 20mhz ? operating modes: synthesizer, jitter attenuator ? operates from a 10mhz to 50mhz fundamental-mode crystal ? initial holdover accuracy of + 50ppb. ? accepts up to 2 lvpecl, lvds, lvhstl or lvcmos input clocks ? accepts frequencies ranging from 8khz to 875mhz ? auto and manual clock select ion with hitless switching ? clock input monitoring including support for gapped clocks ? phase-slope limiting and fully hitless switching options to control output clock phase transients ? generates four lvpecl / lvds / hcsl or eight lvcmos output clocks ? output frequencies ranging from 8khz up to 1.0ghz (differential) ? output frequencies ranging fr om 8khz to 250mhz (lvcmos) ? one integer divider ranging from 4 to 786,420 ? three fractional output dividers (see section, ?output dividers? ) ? programmable loop bandwidth settings from 0.2hz to 6.4khz ? optional fast-lock function ? four general purpose i/o pins wit h optional support for status & control: ? two output enable control inputs provide control over the four clocks ? manual clock selection control input ? lock, holdover and loss-of-signal alarm outputs ? open-drain interrupt pin ? register programmable through i 2 c or via external i 2 c eeprom ? full 2.5v or 3.3v supply modes, 1.8v support for lvcmos outputs, gpio and control pins ? -40c to 85c ambient operating temperature ? package: 40qfn, lead-free (rohs 6)
femtoclock ? ng universal frequency translator 2 revision 1 08/07/15 8T49N241 data sheet 8T49N241 block diagram intn divider fracn feedback pll input clock monitoring, priority, & selection status & control registers gpio logic clk0 otp i 2 c master i 2 c slave reset logic sclk sdata serial eeprom q0 q1 p1 clk1 nint nrst nwp s_a[1:0] gpio 4 fracn divider fracn divider q2 q3 fracn divider osc xtal p0 figure 1. 8T49N241 functional block diagram
40-pin 6mm x 6mm vfqfpn 11 12 13 14 15 16 17 18 19 20 12345678910 31 32 33 34 35 36 37 38 39 40 21222324252627282930 q2 q3 v cco3 v cco2 nq2 gpio[2] nq3 gpio[3] nint v cca clk0 v cc v ee sclk sdata v cc nclk0 clk1 nclk1 s_a1 gpio[0] v cco0 q0 v cca v cca nq0 gpio[1] nq1 q1 v cco1 osco v cca osci v cccs nwp cap cap_ref v cca s_a0 nrst 8T49N241 revision 1 08/07/15 3 femtoclock ? ng universal frequency translator 8T49N241 data sheet pin assignment figure 2. 8T49N241 pinout drawing
femtoclock ? ng universal frequency translator 4 revision 1 08/07/15 8T49N241 data sheet pin description and pin characteristic tables table 1. pin descriptions number name type 1 description 1v cca power analog function supply for core anal og functions. 2.5v or 3.3v supported. 2v cca power analog function supply for analog functi ons associated with the pll. 2.5v or 3.3v supported. 3 gpio[0] i/o pullup general-purpose input-out put. lvttl / lvcm os input levels. 4v cco0 power high-speed output supply for output pair q0, nq0. 2.5v or 3.3v supported for differential output types. lvcmos outputs also support 1.8v. 5 q0 o universal output clock 0. please refer to the section, ?output drivers? for more details. 6 nq0 o universal output clock 0. please refer to the section, ?output drivers? for more details. 7 gpio[1] i/o pullup general-purpose input-out put. lvttl / lvcm os input levels. 8 nq1 o universal output clock 1. please refer to the section, ?output drivers? for more details. 9 q1 o universal output clock 1. please refer to the section, ?output drivers? for more details. 10 v cco1 power high-speed output supply for output pair q1, nq1. 2.5v or 3.3v supported for differential output types. lvcmos outputs also support 1.8v. 11 sdata i/o pullup i 2 c interface bi-directional data. 12 sclk i/o pullup i 2 c interface bi-directional clock. 13 v cc power core digital function supp ly. 2.5v or 3.3v supported. 14 v ee power negative supply voltage. all v ee pins and epad must be connected before any positive supply voltage is applied. 15 v cc power core digital function supp ly. 2.5v or 3.3v supported. 16 clk0 i pulldown non-inverting differential clock input 0. 17 nclk0 i pullup / pulldown inverting differential clock input 0. ? v cc / 2 when left floating (set by internal pullup / pulldown resistors) 18 clk1 i pulldown non-inverting differential clock input 1. 19 nclk1 i pullup / pulldown inverting differential clock input 1. v cc / 2 when left floating (set by internal pullup / pulldown resistors). 20 s_a1 i pulldown i 2 c address bit a1 21 v cco2 power high-speed output supply voltage for output pair q2, nq2. 2.5v or 3.3v supported for differential output types. lvcmos outputs also support 1.8v. 22 q2 o universal output clock 2. please refer to the section, ?output drivers? for more details. 23 nq2 o universal output clock 2. please refer to the section, ?output drivers? for more details. 24 gpio[2] i/o pullup general-purpose input- output. lvttl / lvcm os input levels. 25 nq3 o universal output clock 3. please refer to the section, ?output drivers? for more details. 26 q3 o universal output clock 3. please refer to the section, ?output drivers? for more details. 27 v cco3 power high-speed output supply voltage for output pair q3, nq3. 2.5v or 3.3v supported for differential output types. lvcmos outputs also support 1.8v. 28 gpio[3] i/o pullup general-purpose input- output. lvttl / lvcm os input levels. 29 nint o open-drain with pullup interrupt output. 30 v cca power analog function supply for analog functi ons associated with pll. 2.5v or 3.3v supported. 31 nrst i pullup master reset input. lvttl / lvcmos interface levels: 0 = all registers and state machines are reset to their default values 1 = device runs normally
revision 1 08/07/15 5 femtoclock ? ng universal frequency translator 8T49N241 data sheet 32 v cca power analog function supply for core anal og functions. 2.5v or 3.3v supported. 33 osci i crystal input. accepts a 10 mhz ? 50mhz reference from a clock oscillator or a 12pf fundamental mode, parallel-resonant crystal. 34 osco o crystal output. this pin shou ld be connected to a crystal. if an oscillator is connected to osci, then this pin must be left unconnected. 35 nwp i pullup write protect input. lvttl / lvcmos interface levels. 0 = write operations on the serial port will complete normally, but will have no effect except on interrupt registers. 36 v cccs power output supply for control & status pins: gpio[3:0], sdata, sclk, s_ a1, s_a0, nint, nwp, nrst 1.8v, 2.5v or 3.3v supported 37 cap analog pll external capacitance. 38 cap_ref analog pll external capacitance. 39 v cca power analog function supply for analog functi ons associated with pll. 2.5v or 3.3v supported. 40 s_a0 i pulldown i 2 c address bit a0. epad exposed pad power negative supply voltage. all v ee pins and epad must be connected before any positive supply voltage is applied. note 1: pullup and pulldown refer to internal input resistors. see ta b l e 2 , pin characteristics, for typical values. number name type 1 description table 2. pin characteristics, v cc = v ccox = 3.3v5% or 2.5v5% 1 symbol parameter test conditio ns minimum typical maximum units c in input capacitance 2 3.5 pf r pullup input pullup resistor gpio[3:0], ? nrst, nwp, ? sdata, sclk 51 k ? r pulldown input pulldown resistor s_a0, s_a1 51 k ? c pd power dissipation capacitance ? (per output pair) lvcmos q[0] v ccox = 3.465v 11.5 pf lvcmos q[1:3] v ccox = 3.465v 13 pf lvcmos q[0] v ccox = 2.625v 10.5 pf lvcmos q[1:3] v ccox = 2.625v 16 pf lvcmos q[0] v ccox = 1.89v 11 pf lvcmos q[1:3] v ccox = 1.89v 13 pf lvds, hcsl or lvpecl q[0] v ccox = 3.465v or 2.625v 2.5 pf lvds, hcsl or lvpecl q[1:3] v ccox = 3.465v or 2.625v 4.5 pf r out output ? impedance gpio[3:0] v cccs = 3.3v 26 ? v cccs = 2.5v 30 v cccs = 1.8v 42 lvcmos q[3:0], nq[3:0] v ccox = 3.3v 18 ? v ccox = 2.5v 22 v ccox = 1.8v 30 note 1: v ccox denotes: v cco0, v cco1, v cco2 or v cco3. note 2: this specification does not apply to the osci or osco pins.
femtoclock ? ng universal frequency translator 6 revision 1 08/07/15 8T49N241 data sheet principles of operation the 8T49N241 can be locked to either of the input clocks and generate a wide range of synchronized output clocks. it could be used for example in eith er the tr ansmit or receive path of synchronous ethernet equipment. the 8T49N241 accepts up to two differential or single-ended input cloc ks ranging from 8khz up to 875mhz. it generates up to four output clocks ranging from 8khz up to 1.0ghz. the pll path within the 8T49N241 sup ports three states: lock, holdover and free-run. lock & holdover status may be monitored on register bits and pins. the pll also supports automatic and manual hitless reference switching. in the locked state, the pll locks to a valid clock input and its output clocks have a frequency accuracy equal to the frequency accuracy of the input clock. in the holdover state, the pll will output a clock which is based on the selected holdover behavior. the pll within the 8T49N241 has an initial holdover frequency offset of 50ppb. in the free-run state, the pll outputs a clock with the same frequency accuracy as the external crystal. upon power up, the pll will enter free-run state, in this state it gen erates output clocks with the same frequency accuracy as the external crystal. the 8T49N241 continuously monitors each input for activity (signal transitions). if no input references are provided, the device will remain locked to the crystal in free-run state and will generate output frequencies as a synthesizer. when an input clock has been validated the pll will transition to the loc k state. in automatic reference switching, if the selected input clock fails and there are no other valid input clocks, the pll will quickly detect that and go into holdover. in the holdover state, the pll will output a clock which is based on the selected holdover behavior. if the selected input clock fails and another input clock is available then the 8T49N241 will hitlessly switch to that input clock. the reference switch can be either revertive or non-revertive. manual switchover is also available with switchover only occurring on user command, either via register bit or via the clock select input function of the gpio[3:0] pins. the device supports conversion of any input frequencies to four diff erent independent output frequencies. the 8T49N241 has a programmable loop bandwidth from 0.2hz to 6.4khz. the device monitors all input clocks and generates an alarm when an inp ut clock failure is detected. the device is programmable through an i 2 c and may also autonomously read its register sett ings from an internal one-time programmable (otp) memory or an external serial i 2 c eeprom. crystal input the crystal input on the 8T49N241 is capable of being driven by a parallel-resonant, fundamental mode crystal with a frequency range of 10mhz ? 50mhz. the oscillator input also supports being driven by a single-ended cr ystal oscillator or reference clock. the initial holdover frequency offset is set by the device, but the long te rm drift depends on the quality of the crystal or oscillator attached to this port. this device provides the ability to double the crystal frequency input in to the pll for improved close-in phase noise performance. refer to figure 3 . 0 x2 1 osc register bit dbl_dis to q[2:3] bypass path to analog pll figure 3. doubler block diagram bypass path the crystal input, clk0 or clk1 may be used directly as a clock source for the q[2:3] output dividers. this may only be done for input frequencies of 250mhz or less. input clock selection the 8T49N241 accepts up to two input clocks with frequencies ranging from 8khz up to 875mhz. each input can accept lvpecl, lvds, lvhstl, hcsl or lvcmos inpu ts using 1.8v, 2.5v or 3.3v logic levels. in manual mode, only one of the inputs may be chosen and if that in put fails that pll will enter holdover. manual mode may be operated by directly selecting the desired input ref erence in the refsel register field. it may also operate via pin-selection of the desired input cl ock by selecting that mode in the refsel register field. in that case, gpio[2] must be used as a clock select input (csel). csel = 0 will select the clk0 input and csel = 1 will select the clk1 input. in addition, the crystal frequency may be passed directly to the output di viders q[2:3] for use as a reference. inputs do not support transmission of spread-spectrum clocking source s. since this family is intended for high-performance applications, it will assume input reference sources to have stabilities of + 100ppm or better, except where gapped clock inputs are used.
revision 1 08/07/15 7 femtoclock ? ng universal frequency translator 8T49N241 data sheet if the pll is working in automatic mode, then one of the input reference sources is assigned as the higher priority. at power-up or if the currently selected input reference fails, the pll will switch to the highest priority input reference that is valid at that time (see section, ?input clock monitor? for details). automatic mode has two sub-options: revertive or non-revertive. in revertive mode, the pll will switch to a reference with a higher priority setting whenever one becomes valid. in non-revertive mode the pll remains with the currently selected source as long as it remains valid. the clock input selection is based on the input clock priority set by the clock input priority control bit. input clock monitor each clock input is monitored for loss of signal (los). if no activity has been detected on the clock input within a user-selectable time period then the clock input is considered to be failed and an internal loss-of-signal status flag is set, which may cause an input switchover depending on other settings. the user-selectable time period has sufficient range to allow a gapped clock missing many consecutive edges to be considered a valid input. user-selection of the clock monitor time-period is based on a counter driven by a monitor clock. the monitor clock is fixed at the frequency of the pll?s vco divided by 8. with a vco range of 3ghz - 4ghz, the monitor clock has a frequency range of 375mhz to 500mhz. the monitor logic for each input reference will count the number of monitor clock edges indicated in the appropriate monitor control register. if an edge is received on the input reference being monitored, then the count resets and begins again. if the target edge count is reached before an input reference edge is received, then an internal soft alarm is raised and the count re-starts. during the soft alarm period, the pll tracking will not be adjusted. if an input reference edge is received before the count expires for the second time, then the soft alarm status is cleared and the pll will resume adjustments. if the count expires again without any input reference edge being received, then a loss-of-signal alarm is declared. it is expected that for normal (non -gapped) clock operation, users will set the monitor clock count for each input reference to be slightly longer than the nominal period of that input reference. a margin of 2-3 monitor clock periods should give a reasonably quick reaction time and yet prevent false alarms. for gapped clock operation, the user will set the monitor clock count to a few monitor clock periods longer than the longest expected clock gap period. the monitor count registers support 17-bit count values, which will support at least a gap length of two clock periods for any supported input reference frequency, with longer gaps being supported for faster input reference frequencies. since gapped clocks usually occur on input reference frequencies above 100mhz, gap lengths of thousands of periods can be supported. using this configuration for a gapped clock, the pll will continue to adjust while the normally expected gap is present, but will freeze once the expected gap length has been exceeded and alarm after twice the normal gap length has passed. once a los on any of the input clocks is detected, the appropriate internal los alarm will be asserted and it will remain asserted until that input clock returns and is validated. validation occurs once 8 rising edges have been received on that input reference. if another error condition on the same input clock is detected during the validation time then the alarm remains asserted and the validation period starts over. each los flag may also be reflected on one of the gpio[3:0] outputs. changes in status of any referenc e can also generate an interrupt if not masked. holdover the 8T49N241 supports a small initial holdover frequency offset in non-gapped clock mode. when the input clock monitor is set to support gapped clock operation, this initial holdover frequency offset is indeterminate since the desired behavior with gapped clocks is for the pll to continue to adjust itself even if clock edges are missing. in gapped clock mode, the pll will not enter holdover until the input is missing for two los monitor periods. the holdover performance characteristics of a clock are referred as its accuracy and stability, and are characterized in terms of the fractional frequency offset. the 8T49N241 can only control the initial frequency accuracy. longer-term accuracy and stability are determined by the accuracy and stability of the external oscillator. when the pll loses all valid input references, it will enter the holdover state. in fast average mode, the pll will initially maintain its most recent frequency offset sett ing and then transition at a rate dictated by its selected phase-slo pe limit setting to a frequency offset setting that is based on historical settings. this behavior is intended to compensate for any frequency drift that may have occurred on the input reference before it was detected to be lost. the historical holdover value will have three options: ? return to center of tuning range within the vco band ? instantaneous mode - the holdover frequency will use the dpll current frequency 100msec before it entered holdover. the accuracy is shown in the ac characteristics table, table 11 . ? fast average mode - an internal iir (infinite impulse response) filter is employed to get the frequency offset. the iir filter gives a 3db attenuation point corresponding to nominal a period of 20 minutes. the accuracy is shown in the ac characteristics table, table 11 . when entering holdover, the pll will set a separate internal hold alarm internally. this alarm may be read from internal status register, appear on the appropriate gpio pin and/or assert t he nint output.
femtoclock ? ng universal frequency translator 8 revision 1 08/07/15 8T49N241 data sheet while the pll is in holdover, its freq uency offset is now relative to the crystal input and so the output clocks will be tracing their accuracy to the local oscillator or crystal. at some point in time, depending on the stability & accuracy of that source , the clock(s) will have drifted outside of the limits of the holdove r state and be considered to be in a free-run state. since this borderline is defined outside the pll and dictated by the accuracy and stability of the external local crystal or oscillator, the 8T49N241 cannot know or influence when that transition occurs. input to output clock frequency the 8T49N241 is designed to accept any frequency within its input range and generate four different output frequencies that are independent from the input frequencies and from each other. the internal architecture of the device ensures that most translations will result in the exact output frequency specified. please contact idt for configuration software or other assi stance in determining if a desired configuration will be supported exactly. synthesizer mode operation the device may act as a frequency synthesizer with the pll generating its operating frequency from just the crystal input. by setting the syn_mode register bit and setting the state[1:0] field to freerun, no input clock references are required to generate the desired output frequencies. when operating as a synthesizer , the precision of the output frequency will be < 1ppb for any supported configuration. loop filter and bandwidth the 8T49N241 uses one external capacitor of fixed value to support its loop bandwidth. when operating in synthesizer mode a fixed loop bandwidth of approximately 200khz is provided. when not operating as a synthes izer, the 8T49N241 will support a range of loop bandwidths: 0.2hz, 0. 4hz, 0.8hz, 1.6hz, 3.2hz, 6.4hz, 12hz, 25hz, 50hz, 100hz, 200hz, 400h z, 800hz, 1.6khz or 6.4khz. the device supports two different loop bandwidth settings: acquisition and locked. these loop ban dwidths are selected from the list of options described above. if enabled, the acquisition bandwidth is used while lock is being acquired to allow the pll to ?fast-lock?. once locked the pll will use the locked bandwidth setting. if the acquisition bandwidth setting is not used, the pll will use the locked bandwidth setting at all times. output dividers the 8T49N241 supports one integer output divider and three fractional output dividers. each integer output divider block (q0 only) consists of two divider stages in a series to achieve the desired total output divider ratio. the first stage divider may be set to divide by 4, 5 or 6. the second stage of t he divider may be bypassed (i.e. divide-by-1) or programmed to any even divider ratio from 2 to 131,070. the total divide ratios, settings and possible output frequencies are shown in ta b l e 3 . an output synchronization via the pll_syn bit is necessary after programming the output dividers to ensure that the outputs are synchronized. table 3. output divide ratios fractional output divider programming (q1, q2, q3) for the fracn output dividers q[1:3] , the output divide ratio is given by: ? output divide ratio = (n.f)x2 ? n = integer part: 4, 5, ...(2 18 -1) ? f = fractional part: [0, 1, 2, ...(2 28 -1)]/(2 28 ) for integer operation of these output dividers, n = 3 is also supported for the full output frequency range. the minimum output divide ratio defined above is valid for all clk_sel modes. 1st-stage divide 2nd-stage divide total divide minimum f out mhz maximum f out mhz 4 1 4 750 1000 5 1 5 600 800 6 1 6 500 666.7 4 2 8 375 500 5 2 10 300 400 6 2 12 250 333.3 4 4 16 187.5 250 5 4 20 150 200 6 4 24 125 166.7 ... 4 131,070 524,280 0.0057 0.0076 5 131,070 655,350 0.0046 0.0061 6 131,070 786,420 0.0038 0.0051
revision 1 08/07/15 9 femtoclock ? ng universal frequency translator 8T49N241 data sheet output divider frequency sources output dividers associated with the q[0:1] outputs take their input frequency directly from the pll. output dividers associated with the q[2:3] outputs can take their input frequencies from the pll, clk0 or clk1 input reference frequency or the crystal frequency. output phase control on switchover there are two options on how t he output phase can be controlled when the 8T49N241 enters or leaves the holdover state, or the pll switches between input references. phase-slope limiting or fully hitless switching (sometimes called phase build-out) may be selected. the swmode bit selects which behavior is to be followed. if fully hitless switching is select ed, then the output phase will remain unchanged under any of these conditions. note that fully hitless switching is not supported when external loopback is being used. if phase-slope limiting is selected , then the output phase will adjust from its previous value until it is tracking the new condition at a rate dictated by the slew[1:0] bits. output drivers the q0 to q3 clock outputs are provided with register-controlled output drivers. by selecting the out put drive type in the appropriate register, any of these outputs can support lvcmos, lvpecl, hcsl or lvds logic levels. the operating voltage ranges of each output is determined by its independent output power pin (v cco ) and thus each can have different output voltage levels. output voltage levels of 2.5v or 3.3v are supported for differential operation and lvcmos operation. in addition, lvcmos output o peration supports 1.8v v cco . each output may be enabled or disabl ed by register bits and/or gpio pins. lvcmos operation when a given output is configured to provide lvcmos levels, then both the q and nq outputs will to ggle at the selected output frequency. all the previously descr ibed configuration and control apply equally to both outputs. freque ncy, voltage levels and enable / disable status apply to both the q and nq pins. when configured as lvcmos, the q & nq outputs can be selected to be phase-aligned with each other or inverted relative to one another. selection of phase-alignment may have negative effects on the phase noise performance of any part of the device due to increased simultaneous switching noise within the device. power-saving modes to allow the device to consume the least power possible for a given application, the following functions can be disabled via register programming: ? any unused output, including all output divider logic, can be individually powered-off. ? any unused input, including the clock monitoring logic can be individually powered-off. ? the digital pll can be powered-off when running in synthesizer mode. ? clock gating on logic that is not being used. status / control signals and interrupts the status and control signals for the device, may be operated at 1.8v, 2.5v or 3.3v as determined by the voltage applied to the v cccs pins. all signals will share the same voltage levels. signals involved include: nwp, ni nt, nrst, gpio[3:0], s_a0, s_a1, sclk and sdata. the voltage us ed here is independent of the voltage chosen for the digital and analog core voltages and the output voltages selected for the clock outputs. general-purpose i/os & interrupts the 8T49N241 provides four general purpose input / output (gpio) pins for miscellaneous status & cont rol functions. each gpio may be configured as either an input or an output. each gpio may be directly controlled from register bits or be used as a predefined function as shown in ta b l e 4 . note that the default state prior to configuration being loaded from internal otp will be to set each gpio to input direction to function as an output enable. table 4. gpio configuration if used in the fixed function mode of operation, the gpio bits will reflect the real-time status of their respective status bits as shown in ta bl e 4 . the lol alarm will support two modes of operation: ? de-asserts once pll is locked, or ? de-asserts after pll is locked and all internal synchronization operations that may destabili ze output clocks are completed. gpio pin configured as input configured as output fixed function (default) general purpose fixed function general purpose 3 - gpi[3] lol gpo[3] 2 csel gpi[2] los[0] gpo[2] 1 osel[1] gpi[1] los[1] gpo[1] 0 osel[0] gpi[0] hold gpo[0]
femtoclock ? ng universal frequency translator 10 revision 1 08/07/15 8T49N241 data sheet interrupt functionality interrupt functionality includes an inte rrupt status flag for each of pll loss-of-lock status (lol), pll in holdover status (hold) and loss-of-signal status for each inpu t (los[1:0]). those status flags are set whenever there is an alarm on their respective functions. the status flag will remain set until the alarm has been cleared and a ?1? has been written to the status flag?s register location or if a reset occurs. each status flag will also have an interrupt enable bit that will determine if that status flag is allowed to cause the device interrupt status to be affected (enabled) or not (disabled). all interrupt enable bits will be in t he disabled state after reset. the device interrupt status flag and nint output pin are asserted if any of the enabled interrupt status flags are set. output enable operation when gpio[1:0] are used as output enable control signals, the function of the pins is to select on e of four register-based maps that indicate which outputs should be enabled or disabled. figure 4. output enable map operation device hardware configuration the 8T49N241 supports an internal one-time programmable (otp) memory that can be pre-progra mmed at the factory with one complete device configuration. some or all of this pre-programmed configuration will be loaded into the device?s registers on power-up or reset. these default register settings ca n be over-written using the serial programming interface once reset is complete. any configuration written via the serial programming interface needs to be re-written after any power cycle or reset. pl ease contact idt if a specific factory-programmed configuration is desired. device start-up & reset behavior the 8T49N241 has an internal power-up reset (por) circuit and a master reset input pin nrst. if either is asserted, the device will be in the reset state. for highly programmable devices, it?s common practice to reset the device immediately after the initial power-on sequence. idt recommends connecting the nrst input pin to a programmable logic source for optimal functionality. it is recommended that a minimum pulse width of 10ns be used to drive the nrst input. while in the reset state (nrst input asserted or por active), the device will operate as follows: ? all registers will return to & be held in their default states as indicated in the applicable register description. ? all internal state machines will be in their reset conditions. ? the serial interface will not respond to read or write cycles. ? the gpio signals will be configured as output enable inputs. ? all clock outputs will be disabled. ? all interrupt status and interrupt enable bits will be cleared, negating the nint signal. upon the later of the internal por circuit expiring or the nrst input negating, the device will exit reset and begin self-configuration. the device will load an initial block of its internal registers using the configuration stored in the internal one-time programmable (otp) memory. once this step is complete, the 8T49N241 will check the register settings to see if it should load the remainder of its configuration from an external i 2 c eeprom at a defined address or continue loading from otp, or both. see section, ?i2c boot-up initialization mode? for details on how this is performed. once the full configuration has been loaded, the device will respond to accesses on the serial port and will attempt to lock the pll to the crystal and begin operation. once the pll is locked, all the outputs derived from it will be synchronized and output phase adjustments can then be applied if desired. serial control port description serial control port configuration description the device has a serial control port capable of responding as a slave in an i 2 c compatible configuration, to allow access to any of the internal registers for device programming or examination of internal status. all registers are configured to have default values. see the specifics for each register for details. the device has the additional capabi lity of becoming a master on the i 2 c bus only for the purpose of reading its initial register configurations from a serial eeprom on the i 2 c bus. writing of the configuration to the serial eeprom must be performed by another device on the same i 2 c bus or pre-programmed into the device prior to assembly. en en en en 0 0 q0 dis en en dis 0 1 en dis en dis 1 0 dis dis dis dis 1 1 q1 q2 q3 4 osel[1] osel[0]
revision 1 08/07/15 11 femtoclock ? ng universal frequency translator 8T49N241 data sheet i 2 c mode operation the i 2 c interface is designed to fully support v1.2 of the i 2 c specification for normal and fast mode operation. the device acts as a slave device on the i 2 c bus at 100khz or 400khz using the address defined in the serial interface control register (0006h), as modified by the s_a0 & s_a1 in put pin settings. the interface accepts byte-oriented block write and block read operations. two address bytes specify the register ad dress of the byte position of the first register to write or read. da ta bytes (registers) are accessed in sequential order from the lowest to the highest byte (most significant bit first). read and write block transfers can be stopped after any complete byte transfer. during a write operation, data will not be moved into the registers until the stop bit is received, at which point, all data received in the block write will be written simultaneously. for full electrical i 2 c compliance, it is recommended to use external pull-up resistors for sdata and sclk. the internal pull-up resistors have a size of 51k ? typical. figure 5. i 2 c slave read and write cycle sequencing i 2 c master mode when operating in i 2 c mode, the 8T49N241 has the capability to become a bus master on the i 2 c bus for the purposes of reading its configuration from an external i 2 c eeprom. only a block read cycle will be supported. as an i 2 c bus master, the 8T49N241 will support the following functions: ? 7-bit addressing mode ? base address register for eeprom ? validation of the read block via ccitt-8 crc check against value stored in last byte (84h) of eeprom ? support for 100khz and 400khz operation with speed negotiation. if bit d0 is set at byte address 05h in the eeprom, this will shift from 100khz operation to 400khz operation. ? support for 1- or 2-byte addressing mode ? master arbitration with programmable number of retries ? fixed-period cycle response timer to prevent perm anently hanging the i 2 c bus. ? read will abort with an alarm (bootfail) if any of the following conditions occur: slave nack, arbitration fail, collision during address phase, crc failure, slave response time-out the 8T49N241 will not support the following functions: ?i 2 c general call ? slave clock stretching ?i 2 c start byte protocol ? eeprom chaining ? cbus compatibility ? responding to its own slave address when acting as a master ? writing to external i 2 c devices including the external eeprom used for booting current read s dev addr + r a data 0 a data 1 a a data n p sequential read s dev addr + w a data 0 a data 1 a a data n p offset addr msb a sr dev addr + r a sequential write s dev addr + w a data 0 p a data 1 a a data n a from master to slave from slave to master offset addr lsb a offset addr msb a offset addr lsb a s=start sr = repeated start a=acknowledge a=non \ acknowledge p=stop
femtoclock ? ng universal frequency translator 12 revision 1 08/07/15 8T49N241 data sheet figure 6. i 2 c master read cycle sequencing i 2 c boot-up initialization mode if enabled (via the boot_eep bit in the startup register), once the nrst input has been deasserted (high) and its internal power-up reset sequence has completed, the device will contend for ownership of the i 2 c bus to read its initial register settings from a memory location on the i 2 c bus. the address of that memory location is kept in non-volatile memory in the startup register. during the boot-up process, the device will not respond to serial control port accesses. once the initialization process is complete, the contents of any of the device?s registers can be altered. it is the responsibility of the user to make any desired adjustments in initial values directly in the serial bus memory. if a nack is received to any of the read cycles performed by the device during the initialization process, or if the crc does not match the one stored in address 84h of the eeprom the process will be aborted and any uninitialized registers will remain with their default values. the bootfail bit in the global interrupt status register (0210h) will also be set in this event. contents of the eeprom should be as shown in ta b l e 5 . table 5. external serial eeprom contents sequential read (1 \ byte offset address) s dev addr + w a data 0 a data 1 a a data n p sr dev addr + r a offset addr a sequential read (2 \ byte offset address) s dev addr + w a data 0 a data 1 a a data n p offset addr msb a sr dev addr + r a offset addr lsb a from master to slave from slave to master s=start sr = repeated start a=acknowledge a=non \ acknowledge p=stop eeprom offset (hex) contents d7 d6 d5 d4 d3 d2 d1 d0 00 1111111 1 01 1111111 1 02 1111111 1 03 1111111 1 04 1111111 1 05 1111111 serial eeprom speed select 0 = 100khz 1 = 400khz 06 1 8T49N241 device i 2 c address [6:2] 1 1 07 0000000 0 08 - 83 desired contents of device registers 08h - 83h 84 serial eeprom crc 85 - ff unused
revision 1 08/07/15 13 femtoclock ? ng universal frequency translator 8T49N241 data sheet register descriptions table 6. register blocks register ranges offset (hex) register block description 0000 - 0001 startup control registers 0002 - 0005 device id control registers 0006 - 0007 serial interface control registers 0008 - 002f digital pll control registers 0030 - 0038 gpio control registers 0039 - 003e output driver control registers 003f - 004a output divider cont rol registers (integer portion) 004b - 0056 reserved 0057 - 0062 output divider control registers (fractional portion) 0063 - 0067 output divider so urce control registers 0068- 006b analog pll control registers 006c - 0070 power-down & lock alarm control registers 0071 - 0078 input monitor control registers 0079 interrupt enable register 007a - 007b factory setting registers 007c - 01ff reserved 0200 - 0201 interrupt status registers 0202 - 020b digital pll0status registers 020c general-purpose i nput status register 020d - 0212 global interrupt and boot status register 0213 - 03ff reserved
femtoclock ? ng universal frequency translator 14 revision 1 08/07/15 8T49N241 data sheet table 7a. startup control register bit field locations and descriptions table 7b. device id control register bit field locations and descriptions startup control register block field locations address (hex)d7d6d5d4d3d2 d1 d0 0000 eep_rty[4:0] rsvd nboot_otp nboot_eep 0001 eep_a15 eep_addr[6:0] startup control register block field descriptions bit field name field type default value description eep_rty[4:0] r/w 1h select number of times arbitration for the i 2 c bus to read the se rial eeprom will be retried before being aborted. note that this number does not include the original try. nboot_otp r/w note 1 note 1: these values are specific to the device configuration and can be customized when ordering. please refer to the femtoclo ck ? ng universal frequency translator ordering product informatio n guide or custom datasheet addendum for more details. internal one-time programmable (otp) memory usage on power-up: 0 = load power-up configuration from otp 1 = only load 1st eight bytes from otp nboot_eep r/w note 1 external eeprom usage on power-up: 0 = load power-up configuration from external serial eeprom (overwrites otp values) 1 = don?t use external eeprom eep_a15 r/w note 1 serial eeprom supports 15-bit a ddressing mode (multiple pages). eep_addr[6:0] r/w note 1 i 2 c base address for serial eeprom. rsvd r/w - reserved. always write 0 to this bit location. read values are not defined. device id register control block field locations address (hex)d7d6d5d4d3d2d1d0 0002 rev_id[3:0] dev_id[15:12] 0003 dev_id[11:4] 0004 dev_id[3:0] dash_code [10:7] 0005 dash_code [6:0] 1 device id control register block field descriptions bit field name field type default value description rev_id[3:0] r/w 0h de vice revision. dev_id[15:0] r/w 0606h device id code. dash code [10:0] r/w note 1 note 1: these values are specific to the device configuration and can be customized when ordering. please refer to the femtoclo ck ? ng universal frequency translator ordering product informatio n guide or custom datasheet addendum for more details. device dash code. decimal value assigned by idt to identify the configuration loaded at the factory. ? may be over-written by users at any time.
revision 1 08/07/15 15 femtoclock ? ng universal frequency translator 8T49N241 data sheet table 7c. serial interface control register bit field locations and descriptions serial interface control block field locations address (hex)d7d6d5d4d3d2d1d0 0006 0 uftadd[6:2] uftadd[1] uftadd[0] 0007 rsvd 1 device id control register block field descriptions bit field name field type default value description uftadd[6:2] r/w note 1 note 1: these values are specific to the device configuration a nd can be customized when ordering. generic dash codes -900 thro ugh -902, -998 and -999 are available and programmed with the default i 2 c address of 1111100b. please refer to the femtoclock ng univer- sal frequency translator ordering product information guide for more details. configurable portion of i 2 c base (bits 6:2) address for this device. uftadd[1] r/o 0b i 2 c base address bit 1. this address bit reflec ts the status of the s_a1 external input pin. see table 1. uftadd[0] r/o 0b i 2 c base address bit 0. this address bit reflec ts the status of the s_a0 external input pin. see table 1. rsvd r/w - reserved. always write 0 to this bit location. read values are not defined.
femtoclock ? ng universal frequency translator 16 revision 1 08/07/15 8T49N241 data sheet table 7d. digital pll input control regi ster bit field locations and descriptions digital pll input control register block field locations address (hex)d7d6d5d4d3d2d1d0 0008 refsel[2:0] fbsel[1:0] rvrt swmode 0009 rsvd ref_pri 000a rsvd refdis1 refdis0 rsvd rsvd state[1:0] 000b rsvd pre0[20:16] 000c pre0[15:8] 000d pre0[7:0] 000e rsvd pre1[20:16] 000f pre1[15:8] 0010 pre1[7:0] digital pll input control regi ster block field descriptions bit field name field type default value description refsel[2:0] r/w 000b input reference selection for digital pll: 000 = automatic selection 001 = manual selection by gpio input 010 through 011 = reserved 100 = force selection of input reference 0 101 = force selection of input reference 1 110 = do not use 111 = do not use fbsel[2:0] r/w 000b feedback mode selection for digital pll: 000 through 011 = internal feedback divider 100 = external feedback from input reference 0 101 = external feedback from input reference 1 110 = do not use 111 = do not use rvrt r/w 1b automatic switching mode for digital pll: 0 = non-revertive switching 1 = revertive switching swmode r/w 1b controls how digital pll adjusts output phase when switching between input references: 0 = absorb any phase differences between old & new input references 1 = track to follow new input reference?s phase using phase-slope limiting ref_pri r/w 0b switchover priority for input references when used by digital pll: 0 = clk0 is primary input reference ? 1 = clk1 is primary input reference refdis0 r/w 0b input reference 0 switching selection disable for digital pll: 0 = input reference 0 is includ ed in the switchover sequence 1 = input reference 0 is not incl uded in the switchover sequence refdis1 r/w 0b input reference 1 switching selection disable for digital pll: 0 = input reference 1 is includ ed in the switchover sequence 1 = input reference 1 is not incl uded in the switchover sequence state[1:0] r/w 00b digital pll state machine control: 00 = run automatically 01 = force freerun state - set this if in synthesizer mode. 10 = force normal state 11 = force holdover state
revision 1 08/07/15 17 femtoclock ? ng universal frequency translator 8T49N241 data sheet pre0[20:0] r/w 000000h pre-divider ratio for input reference 0 when used by digital pll. pre1[20:0] r/w 000000h pre-divider ratio for input reference 1 when used by digital pll. rsvd r/w - reserved. always write 0 to this bit location. read values are not defined. digital pll input control regi ster block field descriptions bit field name field type default value description
femtoclock ? ng universal frequency translator 18 revision 1 08/07/15 8T49N241 data sheet table 7e. digital pll feedback control regi ster bit field locations and descriptions digital pll feedback control register block field locations address (hex)d7d6d5d4d3d2d1d0 0011 m1_0[23:16] 0012 m1_0[15:8] 0013 m1_0[7:0] 0014 m1_1[23:16] 0015 m1_1[15:8] 0016 m1_1[7:0] 0017 lckbw[3:0] acqbw[3:0] 0018 lckdamp[2:0] acqdamp[2:0] pllgain[1:0] 0019 rsvd rsvd rsvd rsvd 001a rsvd 001b rsvd 001c rsvd rsvd 001d rsvd 001e rsvd 001f ffh 0020 ffh 0021 ffh 0022 ffh 0023 slew[1:0] rsvd hold[1 :0] rsvd holdavg fastlck 0024 lock[7:0] 0025 rsvd dsm_int[8] 0026 dsm_int[7:0] 0027 rsvd 0028 rsvd dsmfrac[20:16] 0029 dsmfrac[15:8] 002a dsmfrac[7:0] 002b rsvd 002c 01h 002d rsvd 002e rsvd 002f dsm_ord[1:0] dcxogain[ 1:0] rsvd dithgain[2:0]
revision 1 08/07/15 19 femtoclock ? ng universal frequency translator 8T49N241 data sheet digital pll feedback configuration register block field descriptions bit field name field type default value description m1_0[23:0] r/w 070000h m1 feedback divider ratio for input reference 0 when used by digital pll. m1_1[23:0] r/w 070000h m1 feedback divider ratio for input reference 1 when used by digital pll. lckbw[3:0] r/w 0111b digital pll loop bandwidth while locked: 0000 = 0.2hz 0001 = 0.4hz 0010 = 0.8hz 0011 = 1.6hz 0100 = 3.2hz 0101 = 6.4hz 0110 = 12hz 0111 = 25hz 1000 = 50hz 1001 = 100hz 1010 = 200hz 1011 = 400hz 1100 = 800hz 1101 = 1.6khz 1110 = 6.4khz 1111 = reserved acqbw[3:0] r/w 0111b digital pll loop bandwidth while in acquisition (not-locked): 0000 = 0.2hz 0001 = 0.4hz 0010 = 0.8hz 0011 = 1.6hz 0100 = 3.2hz 0101 = 6.4hz 0110 = 12hz 0111 = 25hz 1000 = 50hz 1001 = 100hz 1010 = 200hz 1011 = 400hz 1100 = 800hz 1101 = 1.6khz 1110 = 6.4khz 1111 = reserved lckdamp[2:0] r/w 011b damping factor for digital pll while locked: 000 = reserved 001 = 1 010 = 2 011 = 5 100 = 10 101 = 20 110 = reserved 111 = reserved
femtoclock ? ng universal frequency translator 20 revision 1 08/07/15 8T49N241 data sheet acqdamp[2:0] r/w 011b damping factor for digital pll while in acquisition (not locked): 000 = reserved 001 = 1 010 = 2 011 = 5 100 = 10 101 = 20 110 = reserved 111 = reserved pllgain[1:0] r/w 01b digital loop filter gain settings for digital pll: 00 = 0.5 01 = 1 10 = 1.5 11 = 2 slew[1:0] r/w 00b phase-slope control for digital pll: 00 = no limit - controlled by loop bandwidth of digital pll 01 = 64us/s 10 = 11us/s 11 = reserved hold[1:0] r/w 00b holdover averaging mode selection for digital pll: 00 = instantaneous mode - uses historical value 100ms prior to entering holdover 01 = fast average mode 10 = reserved 11 = return to center of vco tuning range holdavg r/w 0b holdover averaging enable for digital pll: 0 = holdover averaging disabled 1 = holdover averaging enabled as defined in hold[1:0] fastlck r/w 0b enables fast lock operation for digital pll: 0 = normal locking using lckbw & lckdamp fields in all cases 1 = fast lock mode using acqbw & acqdamp when not phase locked and lckbw & lckdamp once phase locked lock[7:0] r/w 3fh lock window size for digital pll. unsigned 2?s complement binary number in steps of 2.5ns, giving a total range of 640ns. do not program to 0. dsm_int[8:0] r/w 02dh integer portion of the delta-sigma modulator value. dsmfrac[20:0] r/w 000000h fractional portion of delta-sigma modu lator value. divide this number by 2 21 to determine the actual fraction. dsm_ord[1:0] r/w 11b delta-sigma modulator order for digital pll: 00 = delta-sigma modulator disabled 01 = 1st order modulation 10 = 2nd order modulation 11 = 3rd order modulation digital pll feedback configuration register block field descriptions bit field name field type default value description
revision 1 08/07/15 21 femtoclock ? ng universal frequency translator 8T49N241 data sheet dcxogain[1:0] r/w 01b multiplier applied to instantaneous frequency e rror before it is applied to the digitally controlled oscillator in digital pll: 00 = 0.5 01 = 1 10 = 2 11 = 4 dithgain[2:0] r/w 000b dither gain setting for digital pll: 000 = no dither 001 = least significant bit (lsb) only 010 = 2 lsbs 011 = 4 lsbs 100 = 8 lsbs 101 = 16 lsbs 110 = 32 lsbs 111 = 64 lsbs rsvd r/w - reserved. always write 0 to this bit location. read values are not defined. digital pll feedback configuration register block field descriptions bit field name field type default value description
femtoclock ? ng universal frequency translator 22 revision 1 08/07/15 8T49N241 data sheet table 7f. gpio control register bit field locations and descriptions the values observed on any gpio pins that are used as general purp ose inputs are visible in the gpi[3:0] register that is locat ed at location 0x0219 near a number of ot her read-only registers. gpio control register block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 0030 rsvd gpio_dir[3:0] 0031 rsvd gpi3sel[2] gpi2sel[2] gpi1sel[2] gpi0sel[2] 0032 rsvd gpi3sel[1] gpi2sel[1] gpi1sel[1] gpi0sel[1] 0033 rsvd gpi3sel[0] gpi2sel[0] gpi1sel[0] gpi0sel[0] 0034 rsvd gpo3sel[2] gpo2sel[2] gpo1sel[2] gpo0sel[2] 0035 rsvd gpo3sel[1] gpo2sel[1] gpo1sel[1] gpo0sel[1] 0036 rsvd gpo3sel[0] gpo2sel[0] gpo1sel[0] gpo0sel[0] 0037 rsvd 0038 rsvd gpo[3:0] gpio control register block field descriptions bit field name field ty pe default value description gpio_dir[3:0] r/w 0000b direction control for general- pur pose i/o pins gpio[3:0]: 0 = input mode 1 = output mode gpi0sel[2:0] r/w 001b function of gpio[0] pin when set to input mode by gpio_dir[0] register bit: 000 = general purpose input (value on gpio[0] pi n dire ctly reflected in gpi[0] register bit) 001 = output enable control bit 0: osel[0], (refer to figure 4 for more details.) 010 = reserved 011 = reserved 100 through 111 = reserved gpi1sel[2:0] r/w 001b function of gpio[1] pin when set to input mode by gpio_dir[1] register bit: 000 = general purpose input (value on gpio[1] pi n dire ctly reflected in gpi[1] register bit) 001 = output enable control bit 1: osel[1], (refer to figure 4 for more details.) 010 through 111 = reserved gpi2sel[2:0] r/w 001b function of gpio[2] pin when set to input mode by gpio_dir[2] register bit: 000 = general purpose input (value on gpio[2] pi n dire ctly reflected in gpi[2] register bit) 001 = csel: manual clock s elect input for pll 010 = reserved 011 = reserved 100 = reserved 101 through 111 = reserved gpi3sel[2:0] r/w 001b function of gpio[3] pin when set to input mode by gpio_dir[3] register bit: 000 = general purpose input (value on gpio[3] pi n dire ctly reflected in gpi[3] register bit) 001 = reserved 010 = reserved 011 = reserved 100 through 111 = reserved
revision 1 08/07/15 23 femtoclock ? ng universal frequency translator 8T49N241 data sheet gpo0sel[2:0] r/w 000b function of gpio[0] pin when set to output mode by gpio_dir[0] register bit: 000 = general purpose output (value in gp o[0] register bit driven on gpio[0] pin 001 = holdover status flag for digital pll reflected on gpio[0] pin 010 = reserved 011 = reserved 100 = reserved 101 = reserved 110 through 111 = reserved gpo1sel[2:0] r/w 000b function of gpio[1] pin when set to output mode by gpio_dir[1] register bit: 000 = general purpose output (value in gp o[1] register bit driven on gpio[1] pin 001 = loss-of-signal status flag for input reference 1 reflected on gpio[1] pin 010 = reserved 011 = reserved 100 = reserved 101 = reserved 110 = reserved 111 = reserved gpo2sel[2:0] r/w 000b function of gpio[2] pin when set to output mode by gpio_dir[2] register bit: 000 = general purpose output (value in gp o[2] register bit driven on gpio[2] pin 001 = loss-of-signal status flag for input reference 0 reflected on gpio[2] pin 010 = reserved 011 = reserved 100 = reserved 101 through 111 = reserved gpo3sel[2:0] r/w 000b function of gpio[3] pin when set to output mode by gpio_dir[3] register bit: 000 = general purpose output (value in gp o[3] register bit driven on gpio[3] pin 001 = loss-of-lock status flag for digital pll reflected on gpio[3] pin 010 = reserved 011 = reserved 100 through 111 = reserved gpo[3:0] r/w 0000b output values reflect on pin gpio[3:0] when general-purpose ou tput mode selected. rsvd r/w - reserved. always write 0 to this bit location. read values are not defined. gpio control register block field descriptions bit field name field type default value description
femtoclock ? ng universal frequency translator 24 revision 1 08/07/15 8T49N241 data sheet table 7g. output driver control regist er bit field locations and descriptions output driver control register block field locations address (hex)d7d6d5 d4 d3d2d1 d0 0039 rsvd outen[3:0] 003a rsvd pol_q[3:0] 003b rsvd 003c rsvd 003d outmode3[2:0] se_mode 3 outmode2[2:0] se_mode2 003e outmode1[2:0] se_mode 1 outmode0[2:0] se_mode0 output driver control regist er block field descriptions bit field name field type default value description outen[3:0] r/w 0000b output enable control for cl ock outputs q[ 3:0], nq[3:0]: 0 = qn is in a high-impedance state 1 = qn is enabled as indicated in appropriate outmoden[2:0] register field pol_q[3:0] r/w 0000b polarity of clock ou tputs q[3:0], nq[3:0]: 0 = qn is normal polarity 1 = qn is inverted polarity outmodem[2:0] r/w 001b output driver mode of operation for clock output pair qm, nqm: 000 = high-impedance 001 = lvpecl 010 = lvds 011 = lvcmos 100 = hcsl 101 - 111 = reserved se_modem r/w 0b behavior of output pair qm, nqm when lvcmos operation is selected: ? (must be 0 if lvds or lvpec l output style is selected) 0 = qm and nqm are both the same frequency but inverted in phase 1 = qm and nqm are both the same frequency and phase rsvd r/w - reserved. always write 0 to this bit location. read values are not defined.
revision 1 08/07/15 25 femtoclock ? ng universal frequency translator 8T49N241 data sheet table 7h. output divider control register (integ er portion) bit field locations and descriptions output divider control register (int eger portion) bl ock field locations address (hex)d7 d6 d5d4d3d2d1d0 003f rsvd ns1_q0[1:0] 0040 ns2_q0[15:8] 0041 ns2_q0[7:0] 0042 rsvd n_q1[17:16] 0043 n_q1[15:8] 0044 n_q1[7:0] 0045 rsvd n_q2[17:16] 0046 n_q2[15:8] 0047 n_q2[7:0] 0048 rsvd n_q3[17:16] 0049 n_q3[15:8] 004a n_q3[7:0] output divider control register (integ er portion) block field descriptions bit field name field type default value description ns1_q0[1:0] r/w 10b 1st stage output divider ratio for output clock q0, nq0: 00 = /5 01 = /6 10 = /4 11 = reserved ns2_q0[15:0] r/w 0002h 2nd stage output divider ratio for output clock q0, nq0. actual divider ratio is 2x the value written here. ? a value of 0 in this register will bypass the second stage of the divider. n_qm[17:0] r/w 20002h integer portion of output divider ratio for output clock qm, nqm (m = 1, 2, 3): values of 0, 1 or 2 cannot be written to this register. ? actual divider ratio is 2x the value written here. rsvd r/w - reserved. always write 0 to this bit location. read values are not defined.
femtoclock ? ng universal frequency translator 26 revision 1 08/07/15 8T49N241 data sheet table 7i. output divider control register (fracti onal portion) bit field locations and descriptions output divider control register (fractional portion) block field locations address (hex)d7 d6 d5d4d3d2d1d0 0057 rsvd nfrac_q1[27:24] 0058 nfrac_q1[23:16] 0059 nfrac_q1[15:8] 005a nfrac_q1[7:0] 005b rsvd nfrac_q2[27:24] 005c nfrac_q2[23:16] 005d nfrac_q2[15:8] 005e nfrac_q2[7:0] 005f rsvd nfrac_q3[27:24] 0060 nfrac_q3[23:16] 0061 nfrac_q3[15:8] 0062 nfrac_q3[7:0] output divider control register (fract ional portion) block field descriptions bit field name field type default value description nfrac_qm[27:0] r/w 0000000h fractional portion of output divider ratio for output clock qm, nqm (m = 1, 2, 3). actual fractional portion is 2x the value written here. ? fraction = (nfrac_qm * 2) * 2 -28 rsvd r/w - reserved. always write 0 to this bit location. read values are not defined.
revision 1 08/07/15 27 femtoclock ? ng universal frequency translator 8T49N241 data sheet table 7j. output clock source control regi ster bit field locations and descriptions output clock source control register block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 0063 pll_syn rsvd clk_sel3[1:0] rsvd rsvd clk_sel2[1:0] 0064 rsvd 0065 rsvd 0066 rsvd rsvd rsvd rsvd 0067 10b 10b 00b rsvd output clock source control register block field descriptions bit field name field type default value description pll_syn r/w 0b output synchronization control for outputs derived from pll. setting this bit from 0->1 will cause the outp ut divider(s) for the a ffected outputs to be held in reset. setting this bit from 1->0 will release all the output divider(s) for the affected outputs to run from the same point in time with the coarse output phase adjustment reset to 0. clk_selm[1:0] r/w 00b clock source selection for output pair qm : nqm (m = 2, 3): do not select input reference 0 or 1 if that input is faster than 250mhz: 00 = pll 01 = input reference 0 (clk0) 10 = input reference 1 (clk1) 11 = crystal input rsvd r/w - reserved. always write 0 to this bit location. read values are not defined.
femtoclock ? ng universal frequency translator 28 revision 1 08/07/15 8T49N241 data sheet table 7k. analog pll control register bit field locations and descriptions please contact idt through one of the methods listed on the last page of this datasheet for details on how to set these fields for a particular user configuration. analog pll control register block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 0068 cpset[2:0] rs[1:0] cp[1:0] wpost 0069 rsvd rsvd tdc_dis syn_mode rsvd dlcnt dbitm 006a vcoman[2:0] dbit[4:0] 006b 001b rsvd analog pll control register block field descriptions bit field name field type default value description cpset[2:0] r/w 100b charge pump current setting for analog pll: 000 = 110a 001 = 220a 010 = 330a 011 = 440a 100 = 550a 101 = 660a 110 = 770a 111 = 880a rs[1:0] r/w 01b internal loop filter series resistor setting for analog pll: 00 = 330 : 01 = 640 : 10 = 1.2k : 11 = 1.79k : cp[1:0] r/w 01b internal loop filter parallel capacitor setting for analog pll: 00 = 40pf 01 = 80pf 10 = 140pf 11 = 200pf wpost r/w 1b internal loop filter 2nd-pole setting for analog pll: 0 = rpost = 497 : , c post = 40pf 1 = rpost = 1.58k : , cpo st = 40pf tdc_dis r/w 0b tdc disable control for pll: 0 = tdc enabled 1 = tdc disabled syn_mode r/w 0b frequency synthesizer mode control for pll: 0 = pll jitter attenuates and translates one or more input references 1 = pll synthesizes output frequencies us ing only the crystal as a reference note that the state[ 1:0] fie ld in the digital pll co ntrol register must be set to force freerun state. dlcnt r/w 1b digital lock count setting for analog pll: 0 = counter is a 20-bit accumulator 1 = counter is a 16-bit accumulator dbitm r/w 0b digital lock manual override setting for analog pll: 0 = automatic mode 1 = manual mode
revision 1 08/07/15 29 femtoclock ? ng universal frequency translator 8T49N241 data sheet table 7l. power down control register bit field locations and descriptions vcoman[2:0] r/w 001b manual lock mode vco selection setting for analog pll: 000 = vco0 001 = vco1 010 = vco2 011 = vco3 100 = vco4 101 = vco5 110 - 111 = reserved dbit[4:0] r/w 01011b manual mode digital lock control setting for vco in analog pll. rsvd r/w - reserved. always write 0 to this bit location. read values are not defined. power down control register block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 006c rsvd lckmode dbl_dis 006d rsvd clk1_dis clk0_dis 006e rsvd 006f rsvd q3_dis q2_dis q1_dis q0_dis 0070 rsvd dpll_dis dsm_dis calrst power down control register block field descriptions bit field name field type default value description lckmode r/w 0b controls the behavior of the lol alarm deassertion: 0 = lol alarm deassert s once pll is locked 1 = lol alarm deasserts once pll is locked and output clocks are stable dbl_dis r/w 0b controls whether crystal input frequen cy is doubled before being used in pll: 0 = 2x actual crystal frequency used 1 = actual crystal frequency used clkm_dis r/w 0b disable control for input reference m (m = 0, 1): 0 = input reference m is enabled 1 = input reference m is disabled qm_dis r/w 0b disable control for output qm, nqm (m = 0, 1, 2, 3): 0 = output qm, nqm functions normally 1 = all logic associated with output qm, nq m is disabled & driver in high-impedance state dpll_dis r/w 0b disable control for digital pll: 0 = digital pll enabled 1 = digital pll disabled dsm_dis r/w 0b disable control for delta-sigma modulator for analog pll: 0 = dsm enabled 1 = dsm disabled calrst r/w 0b reset calibration logic for analog pll: 0 = calibration logic for analog pll enabled 1 = calibration logic for analog pll disabled rsvd r/w - reserved. always write 0 to this bit location. read values are not defined. analog pll control register block field descriptions bit field name field type default value description
femtoclock ? ng universal frequency translator 30 revision 1 08/07/15 8T49N241 data sheet table 7m. input monitor control register bit field locations and descriptions table 7n. interrupt enable control regist er bit field locations and descriptions table 7o. factory setting register bit field locations input monitor control register block field locations address (hex)d7d6d5d4d3d2d1d0 0071 rsvd los_0[16] 0072 los_0[15:8] 0073 los_0[7:0] 0074 rsvd los_1[16] 0075 los_1[15:8] 0076 los_1[7:0] 0077 rsvd 0078 rsvd input monitor control register block field descriptions bit field name field type default va lue description los_m[16:0] r/w 1ffffh number of input monitoring clock periods before input reference m (m = 0, 1) is considered to be missed (soft alarm). minimum setting is 3. rsvd r/w - reserved. always write 0 to this bit location. read values are not defined. interrupt enable control register block field locations address (hex)d7d6 d5 d4d3d2d1d0 0079 rsvd lol_en rsvd hold_en rsvd los1_en los0_en interrupt enable control register block field descriptions bit field name field type default value description lol_en r/w 0b interrupt enable control for loss- of-lock interrupt status bit: 0 = lol_int register bit will not affect status of nint output signal 1 = lol_int register bit will affect status of nint output signal hold_en r/w 0b interrupt enable control for holdover interrupt status bit: 0 = hold_int register bit will not af fect status of nint output signal 1 = hold_int register bit will affe ct status of nint output signal losm_en r/w 0b interrupt enable cont rol for loss-of-signal interrupt status bit for input reference m: 0 = losm_int register bit will not af fect status of ni nt output signal 1 = losm_int register bit will affe ct status of nint output signal rsvd r/w - reserved. always write 0 to this bit location. read values are not defined. factory setting register block field locations address (hex)d7d6 d5 d4d3d2d1d0 007a 27h 007b 000b 1b 0b 1b 0b 0b
revision 1 08/07/15 31 femtoclock ? ng universal frequency translator 8T49N241 data sheet table 7p. interrupt status register bit field locations and descriptions this register contains ?sticky? bits for tracking the status of the various alarms. whenever an alarm occurs, the appropriate i nterrupt status bit will be set. the interrupt status bit will remain asserted even after the original alarm goes away. the interrupt status bits r emain asserted until explicitly cleared by a write of a ?1? to the bit over the serial port. this type of functionality is referred to as read / wri te-1-to-clear (r/w1c). interrupt status register block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 0200 rsvd lol_int rsvd hold_int rsvd los1_int los0_int 0201 rsvd interrupt status register block fi eld de scriptions bit field name field type default value description lol_int r/w1c 0b interrupt status bit for loss-of-lock: 0 = no loss-of-lock alarm flag on pll has occurred since the last time this register bit was cl eared 1 = at least one loss-of-lock alarm flag on pll has occurred since the last time this register bit was cleared hold_int r/w1c 0b interrupt status bit for holdover: 0 = no holdover alarm flag has occurred si nce the last time this register bit was cleared 1 = at least one holdover alarm flag has occurred since the last time this register bit was cleared losm_int r/w1c 0b interrupt status bit for loss-of -si gnal on input reference m: 0 = no loss-of-signal alarm flag on input reference m has occurred since the last tim e this register bit was cleared 1 = at least one loss-of-signal alarm flag on input reference m has occurred since th e last time this register bit was cleared rsvd r/w - reserved. always write 0 to this bit lo cation. read values are not defined. table 7q. general purpose input status re gister bit field locations and descriptions global interrupt status register block field locations address (hex)d7d6d5d4d3d2d1d0 020c rsvd gpi[3] gpi[2] gpi[1] gpi[0] general purpose input status register block field descriptions bit field name field type default value description gpi[3:0] r/o - shows current values on gpio[3:0] pins that are configured as general-purpose inputs. rsvd r/w - reserved. always write 0 to this bit location. read values are not defined.
femtoclock ? ng universal frequency translator 32 revision 1 08/07/15 8T49N241 data sheet table 7r. global interrupt status regist er bit field locations and descriptions global interrupt status register block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 020d rsvd rsvd rsvd int 020e rsvd rsvd 020f rsvd rsvd 0210 rsvd rsvd eep_err bootfail 0211 rsvd rsvd rsvd rsvd rsvd rsvd rsvd eepdone 0212 rsvd global interrupt status register block field descriptions bit field name field type default value description int r/o - device interrupt status: 0 = no interrupt status bits that are enabled are asserted (nint pin released) 1 = at least one interrupt status bit that is enabled is asserted (nint pin asserted low) eep_err r/o - crc mismatch on eeprom read. once set this bit is only cleared by reset. bootfail r/o - reading of serial eeprom failed. once set this bi t is only cleared by reset. eepdone r/o - serial eeprom read cycle has completed. once set this bit is only cleared by reset. rsvd r/w - reserved. always write 0 to this bit location. read values are not defined.
revision 1 08/07/15 33 femtoclock ? ng universal frequency translator 8T49N241 data sheet absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or an y conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. item rating supply voltage, v cc 3.63v inputs, v i osci other input 0v to 2v -0.5v to v cc + 0.5v outputs, v o (q[3:0], nq[3:0]) -0.5v to v ccox 1 + 0.5v outputs, v o (gpio, sclk, sdata, nint) -0.5v to v cccs + 0.5v outputs, i o (q[3:0], nq[3:0]) continuous current surge current 40ma 65ma outputs, i o (gpio[3:0], sclk, sdata, nint) continuous current surge current 8ma 13ma junction temperature, t j 125qc storage temperature, t stg -65 q c to 150 qc supply voltage characteristics table 8a. power supply dc characteristics, v cc = 3.3v 5%, v ee = 0v, t a = -40c to 85c note 1: v ccox denotes: v cco0, v cco1, v cco2, v cco3. symbol parameter test conditio ns minimum typical maximum units v cc core supply voltage 3.135 3.3 3.465 v v cca analog supply voltage 3.135 3.3 v cc v v cccs control and status supply voltage 1.71 v cc v i cc core supply current 1 note 1: i cc, i cca and i cccs are included in i ee when q[3:0] configured for lvpecl logic levels. 39 48 ma i cccs control and status supply current 2 note 2: gpio [3:0], sdata, sclk, s_a1, s_a0, nint, nwp, nrst pins are floating. 3 6ma i cca analog supply current 1 91 121 ma i ee power supply current 3 note 3: internal dynamic switching current at maximum f out is included. q[3:0] configured for lvpecl logic levels; outputs unloaded 281 357 ma
femtoclock ? ng universal frequency translator 34 revision 1 08/07/15 8T49N241 data sheet table 8b. power supply dc characteristics, v cc = 2.5v 5%, v ee = 0v, t a = -40c to 85c symbol parameter test conditio ns minimum typic al maximum units v cc core supply voltage 2.375 2.5 2.625 v v cca analog supply voltage 2.375 2.5 v cc v v cccs control and status supply voltage 1.71 v cc v i cc core supply current 1 note 1: i cc, i cca and i cccs are included in i ee when q[3:0] configured for lvpecl logic levels. 39 47 ma i cccs control and status supply current 2 note 2: gpio [3:0], sdata, sclk, s_a1, s_a0, nint, nwp, nrst pins are floating. 3 5ma i cca analog supply current 1 87 118 ma i ee power supply current 3 note 3: internal dynamic switching current at maximum f out is included. q[3:0] configured for lvpecl logic levels. outputs unloaded 264 337 ma table 8c. maximum output supply current, v cc = v cccs = 3.3v 5% or 2.5v 5%, v ee = 0v, t a = -40c to 85c symbol parameter test conditions v ccox 1 = 3.3v 5% note 1: v ccox denotes v cco0, v cco1, v cco2, v cco3. v ccox 1 = 2.5v 5% v ccox 1 = 1.8v5% units lvpecl lvds hcsl lvcmos lvpecl lvds hcsl lvcmos lvcmos i cco0 2 note 2: internal dynamic switching current at maximum f out is included. q0, nq0 output ? supply current outputs unloaded 41 50 41 44 35 42 36 35 30 ma i cco1 2 q1, nq1 output ? supply current outputs unloaded 55 64 55 55 48 57 47 52 43 ma i cco2 2 q2, nq2 output ? supply current outputs unloaded 56 66 56 56 49 58 49 53 44 ma i cco3 2 q3, nq3 output ? supply current outputs unloaded 57 65 56 57 49 57 51 53 44 ma
revision 1 08/07/15 35 femtoclock ? ng universal frequency translator 8T49N241 data sheet dc electrical characteristics table 8e. differential input dc characteristics, v cc = 3.3v 5% or 2.5v 5%, v ee = 0v, t a = -40c to 85c table 8d. lvcmos/lvttl dc characteristics, v cc = 3.3v 5% or 2.5v 5%, v ee = 0v, t a = -40c to 85c symbol parameter test conditio ns minimum typical maximum units v ih input high voltage nwp, nrst, ? gpio[3:0], sdata, sclk, s_a1, s_a0 v cccs = 3.3v 2.1 v cccs +0.3 v v cccs = 2.5v 1.7 v cccs +0.3 v v cccs = 1.8v 1.4 v cccs +0.3 v v il input low voltage nwp, nrst, ? gpio[3:0], sdata, sclk, s_a1, s_a0 v cccs = 3.3v -0.3 0.8 v v cccs = 2.5v -0.3 0.6 v v cccs = 1.8v -0.3 0.4 v i ih input high current s_a1, s_a0 v cccs = v in = 3.465v, 2.625v, 1.89v 150 ? a nrst, nwp, ? sdata, sclk v cccs = v in = 3.465v, 2.625v, 1.89v 5 ? a gpio[3:0] v cccs = v in = 3.465v, 2.625v, 1.89v 1 ma i il input low current s_a1, s_a0 v cccs = 3.465v, 2.625v, 1.89v, v in = 0v -5 ? a nrst, nwp, ? sdata, sclk v cccs = 3.465v, 2.625v, 1.89v, v in = 0v -150 ? a gpio[3:0] v cccs = 3.465v, 2.625v, 1.89v, v in = 0v -1 ma v oh output high voltage sdata 1 , sclk 1 , nint 1 note 1: use of external pull-up resistors is recommended. v cccs = 3.3v 5%, i oh = -5a 2.6 v gpio[3:0] v cccs = 3.3v 5%, i oh = -50a 2.6 v sdata 1 , sclk 1 , nint 1 v cccs = 2.5v 5%, i oh = -5a 1.8 v gpio[3:0] v cccs = 2.5v 5%, i oh = -50a 1.8 v sdata 1 , sclk 1 , nint 1 v cccs = 1.8v 5%, i oh = -5a 1.3 v gpio[3:0] v cccs = 1.8v 5%, i oh = -50a 1.3 v v ol output low voltage sdata 1 , sclk 1 , nint 1 v cccs = 3.3v 5%, 2.5v5%, or 1.8v5% i ol = 5ma 0.5 v gpio[3:0] v cccs = 3.3v 5%, 2.5v5%, or 1.8v5% i ol = 5ma 0.5 v symbol parameter test conditio ns minimum typical maximum units i ih input high current clkx, 1 nclkx 1 note 1: clkx denotes clk0, clk1. nclkx denotes nclk0, nclk1. v cc = v in = 3.465v or 2.625v 150 ? a i il input low current clkx 1 v cc = 3.465v or 2.625v, v in = 0v -5 ? a nclkx 1 v cc = 3.465v or 2.625v, v in = 0v -150 ? a v pp peak-to-peak voltage 2 note 2: v il should not be less than -0.3v. v ih should not be higher than v cc. 0.15 1.3 v v cmr common mode input voltage 2, 3 note 3: common mode voltage is defined as the cross-point. v ee v cc -1.2 v
femtoclock ? ng universal frequency translator 36 revision 1 08/07/15 8T49N241 data sheet table 8f. lvpecl dc characteristics, v cc = 3.3v 5% or 2.5v 5%, v ee = 0v, t a = -40c to 85c symbol parameter test conditions v ccox 1 = 3.3v5% note 1: v ccox denotes v cco0, v cco1, v cco2, v cco3. v ccox 1 = 2.5v5% units minimum typical maximum m inimum typical maximum v oh output high voltage 2 note 2: outputs terminated with 50 ? to v ccox ? 2v. v ccox - 1.3 v ccox - 0.8 v ccox - 1.4 v ccox - 0.9 v v ol output low voltage 2 v ccox - 1.95 v ccox - 1.75 v ccox - 1.95 v ccox - 1.75 v table 8g. lvds dc characteristics, v cc = 3.3v 5% or 2.5v 5%, v ccox = 3.3v 5% or 2.5v 5%, v ee = 0v, ? t a = -40c to 85c 1, 2 note 1: v ccox denotes v cco0, v cco1, v cco2, v cco3. note 2: terminated with 100 ? across qx and nqx. symbol parameter test conditio ns minimum typical maximum units v od differential output voltage 200 400 mv ? v od v od magnitude change 50 mv v os offset voltage 1.1 1.375 v ? v os v os magnitude change 50 mv table 8h. lvcmos dc characteristics, v cc = 3.3v 5% or 2.5v 5%, v ee = 0v, t a = -40c to 85c symbol parameter test conditions v ccox 1 = 3.3v5% note 1: v ccox denotes v cco0, v cco1, v cco2, v cco3. v ccox 1 = 2.5v5% v ccox 1 = 1.8v 5% units minimum typical maximum minimum typical maximum minimum typical maximum v oh output ? high voltage i oh = -8ma 2.6 1.8 1.1 v v ol output ? low voltage i ol = 8ma 0.5 0.5 0.5 v
revision 1 08/07/15 37 femtoclock ? ng universal frequency translator 8T49N241 data sheet table 9. input frequency characteristics, v cc = 3.3v5% or 2.5v5%, t a = -40c to 85c table 10. crystal characteristics symbol parameter test conditions minimum typical maximum units f in input frequency 1 note 1: for the input reference frequency, the divider values must be set for the vco to operate within its supported range. osci, osco using a crystal (see table 10 for crystal characteristics) 10 50 mhz over-driving crystal input doubler logic enabled 2 note 2: for optimal noise performance, the use of a quartz crystal is recommended. refer to section, ?overdriving the xtal interface? in the applications information section. 10 62.5 mhz over-driving crystal input doubler logic disabled 2 10 125 mhz clkx, 3 nclkx 3 note 3: clkx denotes clk0, clk1; nclkx denotes nclk0, nclk1. 0.008 875 mhz f pd phase detector frequency 4 note 4: pre-dividers must be used to divide the clkx frequency down to a f pd valid frequency range. 0.008 8 mhz f sclk serial port clock sclk (slave mode) i 2 c operation 100 400 khz parameter test conditions mi nimum typical maximum units mode of oscillation fundamental frequency 10 50 mhz equivalent series resistance (esr) 15 30 ? load capacitance (c l ) 12 pf frequency stability (total) -100 100 ppm
femtoclock ? ng universal frequency translator 38 revision 1 08/07/15 8T49N241 data sheet ac electrical characteristics table 11. ac characteristics, v cc = 3.3v 5% or 2.5v 5%, v ccox = 3.3v 5%, 2.5v 5% or 1.8v 5% (1.8v only supported for lvcmos outputs), t a = -40c to 85c 1, 2 symbol parameter test conditio ns minimum typical maximum units f vco vco operating frequency 3000 4000 mhz f out output frequency lvpecl, lvds, hcsl integer divide ratio 0.008 1000 mhz q1, q2, q3 outputs non-integer divide 0.008 400 mhz lvcmos 0.008 250 mhz t r / t f output rise and fall times lvpecl 20% to 80% 320 520 ps lvds 20% to 80%, v ccox = 3.3v 160 320 ps 20% to 80%, v ccox = 2.5v 200 400 ps hcsl 20% to 80% 280 470 ps lvcmos 3, 4 20% to 80%, v ccox = 3.3v 240 310 ps 20% to 80%, v ccox = 2.5v 260 330 ps 20% to 80%, v ccox = 1.8v 350 550 ps sr output slew rate lvpecl differential waveform, measured 150mv from center 15v/ns lvds differential waveform, measured 150mv from center, v ccox = 2.5v 0.5 4 v/ns differential waveform, measured 150mv from center, v ccox = 3.3v 0.5 5 v/ns hcsl measured on differential waveform, 150mv from center, v ccox = 2.5v, f out ? 156.25mhz 1.5 5 v/ns measured on differential waveform, 150mv from center, v ccox = 3.3v, f out ? 156.25mhz 2.5 6.5 v/ns odc output duty cycle 5 lvpecl, ? lvds, hcsl f out ? 666.667mhz 45 50 55 % lvpecl, ? lvds, hcsl f out > 666.667mhz 40 50 60 % lvcmos 40 50 60 % ? spo static phase offset variation 6 f in = f out = 156.25mhz, v cc = v ccox = 2.5v5% or 3.3v5% -350 350 ps initial frequency offset 7, 8, 9 switchover or entering / leaving holdover state -50 50 ppb output phase change in ? fully hitless switching 8, 9, 10 switchover or entering / leaving holdover state 2ns
revision 1 08/07/15 39 femtoclock ? ng universal frequency translator 8T49N241 data sheet ? ssb (1k) single sideband ? phase noise 11 1khz 122.88mhz output -102 dbc/hz ? ssb (10k) 10khz 122.88mhz output -131 dbc/hz ? ssb (100k) 100khz 122.88mhz output -133 dbc/hz ? ssb (1m) 1mhz 122.88mhz output -144 dbc/hz ? ssb (10m) 10mhz 122.88mhz output -154 dbc/hz ? ssb (30m) > 30mhz 122.88mhz output -157 dbc/hz spurious limit at offset 12 > 800khz 122.88mhz lvpecl output -77 dbc t startup startup time internal otp startup 8 from v cc >80% to first output clock edge 110 150 ms external eeprom startup 8, 13 from v cc >80% to first output clock edge (0 retries) i 2 c frequency = 100khz 120 200 ms from v cc >80% to first output clock edge (0 retries) i 2 c frequency = 400khz 110 150 ms from v cc >80% to first output clock edge (31 retries) i 2 c frequency = 100khz 610 1200 ms from v cc >80% to first output clock edge (31 retries) i 2 c frequency = 400khz 270 500 ms note 1: v ccox denotes v cco0, v cco1, v cco2, v cco3. note 2: electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflo w greater than 500 lfpm. the device will meet specifications after thermal equilibrium has been reached under these conditions. note 3: appropriate se_mode bit must be configured to select phase-aligned or phase-inverted operation. note 4: all q and nq outputs in phase-inverted operation. note 5: characterized in pll mode. duty cycle of bypassed signa ls (input reference clocks or crystal input) is not adjusted by the device. note 6: this parameter was measured using clk0 as the reference input and clk1 as the external feedback input. characterized wi th 8T49N241-902. note 7: tested in fast-lock operation after >20 minutes of lo cked operation to ensure holdover averaging logic is stable. note 8: this parameter is guaranteed by design. note 9: using internal feedback mode configuration. note 10: device programmed with swmode = 0 (absorbs phase differences). note 11: characterized with 8T49N241-900. note 12: tested with all output s operating at 122.88mhz, integer output divider mode. note 13: assuming a clear i 2 c bus. table 11. ac characteristics, v cc = 3.3v 5% or 2.5v 5%, v ccox = 3.3v 5%, 2.5v 5% or 1.8v 5% (1.8v only supported for lvcmos outputs), t a = -40c to 85c 1, 2 (continued) symbol parameter test conditio ns minimum typical maximum units
femtoclock ? ng universal frequency translator 40 revision 1 08/07/15 8T49N241 data sheet table 12. hcsl ac characteristics, v cc = 3.3v 5% or 2.5v 5%, v ccox = 3.3v 5% or 2.5v 5%, t a = -40c to 85c 1, 2 symbol parameter test conditio ns minimum typical maximum units v rb ring-back voltage margin 3, 4 -100 100 mv t stable time before v rb is allowed 3, 4 500 ps v max absolute max. output voltage 5, 6 1150 mv v min absolute min. output voltage 5, 7 -300 mv v cross absolute crossing voltage 8, 9 200 500 mv ? v cross total variation of v cross over all edges 8, 10 140 mv note 1: electrical parameters are guaranteed over the specifie d ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. the device will meet specifications after thermal equilibrium has been reached under these conditions. note 2: v ccox denotes v cco0, v cco1, v cco2, v cco3. note 3: measurement taken from differential waveform. note 4: t stable is the time the differential clock must maintain a minimum 150mv differential voltage after rising/falling edges before it is allowed to drop back into the v rb 100mv differential range. note 5: measurement taken from single ended waveform. note 6: defined as the maximum instantaneous voltage including overshoot. note 7: defined as the minimum instantaneous voltage including undershoot. note 8: measured at crossing point where the instantaneous voltage value of the risi ng edge of qx equals the falling edge of nq x. note 9: refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. refe rs to all crossing points for this measurement. note 10: defined as the total variation of all crossing voltages of rising qx and falling nqx, this is the maximum allowed vari ance in v cross for any particular system. table 13a. typical rms phase jitter, v cc = 3.3v 5% or 2.5v 5%, v ccox = 3.3v 5%, 2.5v 5% or 1.8v 5% (1.8v only supported for lvcmos outputs), t a = -40c to 85c 1 symbol parameter test conditio ns lvpecl lvds hcsl lvcmos units tjit( ? ) rms phase jitter 2 (random) q0 f out = 122.88mhz,integration range 12khz - 20mhz 3, 4 322 340 332 359 fs q1, q2, q3 integer f out = 122.88mhz, integration range: 12khz - 20mhz 3, 4 350 377 348 383 fs q1, q2, q3 fractional f out = 122.88mhz, integration range: 12khz - 20mhz 3, 5 317 371 315 356 fs note 1: v ccox denotes v cco0, v cco1, v cco2, v cco3. note 2: it is recommended to use idt?s timing commander software to program the device for optimal jitter performance. note 3: tested with all outputs oper ating at the same output frequency. note 4: characterized with 8T49N241-900. note 5: characterized with 8T49N241-901.
revision 1 08/07/15 41 femtoclock ? ng universal frequency translator 8T49N241 data sheet table 13b. pci express jitter specifications, v cc = v ccox = 3.3v 5% or 2.5v 5%, t a = -40c to 85c 1, 2 symbol parameter test conditions 3 minimum typical maximum pcie industry specification units t j (pcie gen 1) phase jitter peak-to-peak 4, 5 ? = 100mhz, 40mhz crystal input evaluation band: 0hz - nyquist (clock frequency/2) 10.1 52 86 ps t refclk_hf_rm s (pcie gen 2) phase jitter rms 5, 6 ? = 100mhz, 40mhz crystal input high band: 1.5mhz - nyquist (clock frequency/2) 0.51 1.5 3.1 ps t refclk_lf_rms (pcie gen 2) phase jitter rms 5, 6 ? = 100mhz, 40mhz crystal input low band: 10khz - 1.5mhz 0.03 0.5 3.0 ps t refclk_rms (pcie gen 3) phase jitter rms 5, 7 ? = 100mhz, 40mhz crystal input evaluation band: 0hz - nyquist (clock frequency/2) 0.10 0.5 0.8 ps note 1: v ccox denotes v cco0, v cco1, v cco2, v cco3. note 2: electrical parameters are guaranteed over the specifi ed ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. the device will meet specifications after thermal equilibrium has been reached under these conditions. note 3: outputs configured in hcsl mode. fox # 277lf-40-18 crystal used with doubler logic enabled. note 4: peak-to-peak jitter after applyi ng system transfer function for the common clo ck architecture. maximum limit for pci ex press gen 1 note 5: this parameter is guaranteed by characterization. not tested in production. note 6: rms jitter after applying the two evaluation bands to the two transfer functions defined in the common clock architectu re and ? reporting the worst case results for each evaluation band. ma ximum limit for pci express generation 2 is 3.1ps rms for ? t refclk_hf_rms (high band) and 3.0ps rms for t refclk_lf_rms (low band). note 7: rms jitter after applying system transfer function for the common clock architecture. this specification is based on th e pci express base specification revision 0.7, october 2009 and is subject to change pending the final release version of the specification.
femtoclock ? ng universal frequency translator 42 revision 1 08/07/15 8T49N241 data sheet typical phase noise at 122.88mhz noise power dbc ? hz offset frequency (hz)
revision 1 08/07/15 43 femtoclock ? ng universal frequency translator 8T49N241 data sheet applications information recommendations for unused input and output pins i nputs: clkx/nclkx input for applications not requiring the us e of one or more reference clock inputs, both clkx and nclkx can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from clkx to ground. it is recommende d that clkx, nclkx not be driven with active signals when not selected. lvcmos control pins all control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. outputs: lvpecl outputs any unused lvpecl output pair can be left floating. we recommend that there is no trace attached. bo th sides of the differential output pair should either be left floating or terminated. lv d s o u t p u t s any unused lvds output pair can be ei ther left floating or terminated with 100 ? across. if they are left floating there should be no trace attached. lvcmos outputs any lvcmos output can be left floating if unused. there should be no trace attached. hcsl outputs all unused differential outputs c an be left floating. we recommend that there is no trace attached. bo th sides of the differential output pair should either be left floating or terminated.
femtoclock ? ng universal frequency translator 44 revision 1 08/07/15 8T49N241 data sheet overdriving the xtal interface the osci input can be overdriven by an lvcmos driver or by one side of a differential driver through an ac coupling capacitor. the osco pin can be left floating. the amplitude of the input signal should be between 500mv and 1.8v and the slew rate should not be less than 0.2v/ns. for 3.3v lvcmos inputs, the amplitude must be reduced from full swing to at least half the swing in order to prevent signal interference with the power rail and to reduce internal noise. figure 7a shows an example of the interface diagram for a high speed 3.3v lvcmos driver. this c onfiguration requires that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the crystal input will attenuate the signal in half. this can be done in one of two ways. first, r1 and r2 in parallel should equal the transmission line impedance. for most 50 ? applications, r1 and r2 can be 100 ? . this can also be accomplished by removing r1 and changing r2 to 50 ? . the values of the resistors can be increased to reduce the loading for a slower and weaker lvcmos driver. figure 7b shows an example of the interface diagram for an lvpecl driver. this is a standard lvpecl termination with one side of the driver feeding the osci input. it is recommended that all components in the schematics be placed in the layout. though some components might not be used, they can be utilized for debugging purposes. the datasheet specifications are characterized and guaranteed by using a quartz crystal as the input. figure 7a. general diagram for lvcmos driver to xtal input interface figure 7b. general diagram for lvpec l driver to xtal input interface lvcmo s _driver zo = 50 r s zo = ro + r s ro r2 100 r1 100 vcc o s co o s ci c1 0.1 f lvpecl_driver zo = 50 r2 50 r 3 50 c2 0.1 f o s co o s ci zo = 50 r1 50
revision 1 08/07/15 45 femtoclock ? ng universal frequency translator 8T49N241 data sheet wiring the differential input to accept single-ended levels figure 8 shows how a differential input can be wired to accept single ended levels. the reference voltage v ref = v cc /2 is generated by the bias resistors r1 and r2. the bypass capacitor (c1) is used to help filter noise on the dc bias. this bias circuit should be located as close to the input pin as possible. the ratio of r1 and r2 might need to be adjusted to position the v ref in the center of the input voltage swing. for example, if the input clock swing is 2.5v and v cc = 3.3v, r1 and r2 value should be adjusted to set v ref at 1.25v. the values below are for when both the single ended swing and v cc are at the same voltage. this configuration requ ires that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the input will attenuate the signal in half. this can be done in one of two ways. first, r3 and r4 in parallel should equal the transmission line impedance. for most 50 ? applications, r3 and r4 can be 100 ? . the values of the resistors can be increased to reduce the loading for slower and weaker lvcmos driver. when using single-ended signaling, the noise rejection bene fits of differential signaling are reduced. even though the differential input can handle full rail lvcmos signaling, it is recommended that the amplitude be reduced. the datasheet specifies a lower differential amplitude, however this only applies to differential signals. for single-ended applications, the swing can be larger, however v il cannot be less than -0.3v and v ih cannot be more than v cc + 0.3v. suggest edge rate faster than 1v/ns. though some of the recommended components might not be used, th e pads should be placed in the layout. they can be utilized for debugging purposes. the datasheet specifications are characteri zed and guaranteed by using a differential signal. figure 8. recommended schematic for wiring a diff erential input to accept single-ended levels
femtoclock ? ng universal frequency translator 46 revision 1 08/07/15 8T49N241 data sheet 3.3v differential clock input interface clkx/nclkx accepts lvds, lvpecl, lvhstl, hcsl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figure 9a to figure 9e show interface examples for the clkx/nclkx input driven by the most common driver types. the input interfaces suggested here are examples only. please consult with the vendor of t he driver component to confirm the driver termination requirements. for example, in figure 9a , the input termination applies for idt open emitter lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. figure 9a. clkx/nclkx input driven by an ? idt open emitter lvhstl driver figure 9b. clkx/nclkx input driven by a ? 3.3v lvpecl driver figure 9c. clkx/nclkx input driven by a ? 3.3v hcsl driver figure 9d. clkx/nclkx input driven by a ? 3.3v lvpecl driver figure 9e. clkx/nclkx input driven by a ? 3.3v lvds driver r1 50 r2 50 1.8v zo = 50 zo = 50 clk nclk 3.3v lvhstl idt lvhstl driver differential input h csl *r 3 * r4 c l k n c l k 3 . 3v 3 . 3v diff e r e nti a l in p u t
revision 1 08/07/15 47 femtoclock ? ng universal frequency translator 8T49N241 data sheet 2.5v differential clock input interface clkx/nclkx accepts lvds, lvpecl, lvhstl, hcsl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figure 10a to figure 10e show interface examples for the clkx/nclkx input driven by the most common driver types. the input interfaces suggested here are examples only. please consult with the vendor of t he driver component to confirm the driver termination requirements. for example, in figure 10a , the input termination applies for idt open emitter lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. figure 10a. clkx/nclkx input driven by an ? idt open emitter lvhstl driver figure 10b. clkx/nclkx input driven by a ? 2.5v lvpecl driver figure 10c. clkx/nclkx input driven by a ? 2.5v hcsl driver figure 10d. clkx/nclkx input driven by a ? 2.5v lvpecl driver figure 10e. clkx/nclkx input driven by a ? 2.5v lvds driver r1 50 ? r2 50 ? 1. 8v zo = 50 ? ? s l * r 333 * r4 33 clk nclk 2.5v 2.5v zo = 50 zo = 50 differenti a l inp u t r1 50 r2 50 * option a l ? r 3 a nd r4 c a n b e 0
femtoclock ? ng universal frequency translator 48 revision 1 08/07/15 8T49N241 data sheet lvds driver termination for a general lvds interface, the recommended value for the termination impedance (z t ) is between 90 ? and 132 ? . the actual value should be selected to match the differential impedance (z 0 ) of your transmission line. a typical point-to-point lvds design uses a 100 ? parallel resistor at the receiver and a 100 ? differential transmission-line environment. in order to avoid any transmission-line reflection issues, the components should be surface mounted and must be placed as close to the receiver as possible. idt offers a full line of lvds compliant devices with two types of output struct ures: current source and voltage source. the standard termination schematic as shown in figure 11a can be used with either type of output structure. figure 11b , which can also be used with both output types, is an optional termination with center tap capacitance to help filter comm on mode noise. the capacitor value should be approximately 50pf. if using a non-standard termination, it is recommended to contact idt and confirm if the out put structure is current source or voltage source type. in addition, since these outputs are lvds compatible, the input receiver?s amplitude and common-mode input range should be verified for compatibility with the output. figure 11a. standard lvds termination figure 11b. optional lvds termination lv d s driver z o ? z t z t lv d s receiver lv d s driver z o ? z t lv d s receiver c z t 2 z t 2
revision 1 08/07/15 49 femtoclock ? ng universal frequency translator 8T49N241 data sheet termination for 3.3v lvpecl outputs the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. the differential output s generate ecl/lvpecl compatible outputs. therefore, terminating resistors (dc current path to ground) or current sources must be used for functionality. t hese outputs are designed to drive 50 ? transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figure 12a and figure 12b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. figure 12a. 3.3v lvpecl ou tput termination figure 12b. 3. 3v lvpecl output termination r1 84 ? r2 84 ? 3.3v r3 125 ? r4 125 ? z o = 50 ? z o = 50 ? input 3.3v 3.3v + _
femtoclock ? ng universal frequency translator 50 revision 1 08/07/15 8T49N241 data sheet termination for 2.5v lvpecl outputs figure 13a and figure 13c show examples of termination for 2.5v lvpecl driver. these terminations are equivalent to terminating 50 ? to v cco ? 2v. for v cco = 2.5v, the v cco ? 2v is very close to ground level. the r3 in figure 13c can be eliminated and the termination is shown in figure 13b . figure 13a. 2.5v lvpecl dr iver termination example figure 13b. 2.5v lvpecl dr iver termination example figure 13c. 2.5v lvpecl driver termination example 2.5v lvpecl driver v cco = 2.5v 2.5v 2.5v 50 ? 50 ? r1 250 r3 250 r2 62.5 r4 62.5 + ? 2.5v lvpecl driver v cco = 2.5v 2.5v 50 ? 50 ? r1 50 r2 50 + ? 2.5v lvpecl driver v cco = 2.5v 2.5v 50 ? 50 ? r1 50 r2 50 r3 18 + ?
revision 1 08/07/15 51 femtoclock ? ng universal frequency translator 8T49N241 data sheet hcsl recommended termination figure 14a is the recommended source termination for applications where the driver and receiver will be on a separate pcbs. this termination is the standard for pci express? and hcsl output types. all traces should be 50 ? impedance single-ended or 100 ? differential. figure 14a. recommended source termination (where th e driver and receiver will be on separate pcbs) figure 14b is the recommended termination for applications where a point-to-point connection can be used. a point-to-point connection contains both the driver and the receiver on the same pcb. with a matched termination at the receiver, transmission-line reflections will be minimized. in addition, a series resistor (rs) at the driver offers flexibility and can help dampen unwanted reflections. the optional resistor can range from 0 ? to 33 ? . all traces should be 50 ? impedance single-ended or 100 ? differential. figure 14b. recommended termination (where a point-to-point connection can be used) 0-0.2" pci express l1 l1 1-14" driver rs 0.5" max l3 l4 l2 l2 49.9 +/- 5% 22 to 33 +/-5% rt l3 l4 l5 0.5 - 3.5" l5 connector pci express add-in card pci express 0-0.2" pci express 0-0.2" 0-18" l1 l1 rs driver 0.5" max l3 l3 l2 l2 49.9 +/- 5% 0 to 33 0 to 33 rt
femtoclock ? ng universal frequency translator 52 revision 1 08/07/15 8T49N241 data sheet vfqfn epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 15 . the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are nece ssary to effectively conduct from the surface of the pcb to the gro und plane(s). the land pattern must be connected to ground through thes e vias. the vias act as ?heat pipes?. the number of vias (i.e. ?h eat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requirement s. thus, thermal and electrical analysis and/or testing are reco mmended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended t hat the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal la nd. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, please refer to the application note on the surface mount assembly of amkor?s thermally/ electrically enhance lead frame base package, amkor technology. figure 15. p.c. assembly for exposed pad thermal release path ? side view (drawing not to scale) schematic and layout information schematics for the 8T49N241 can be found on idt.com. please search for the 8T49N241 device and click on the link for evaluation board. the evaluation board user guide includes schematic and layout information. crystal recommendation this device was validated using fox 277lf series through-hole crystals including part # 277lf-40-18 (40mhz). if a surface mount crystal is desired, we recommend idt part # 603-40-48 (40mhz) and fox part #603-40-48 (40mhz). solder solder pin pin exposed heat slug pin pad pin pad ground plane land pattern (ground pad) thermal via
revision 1 08/07/15 53 femtoclock ? ng universal frequency translator 8T49N241 data sheet pci express application note pci express jitter analysis methodology models the system response to reference clock jitter. the block diagram below shows the most frequently used common clock architecture in which a copy of the reference clock is provided to both ends of the pci express link. in the jitter analysis, the transmit (tx) and receiv e (rx) serdes plls are modeled as well as the phase in terpolator in the receiver. these transfer functions are called h1, h2, and h3 respectively. the overall system transfer function at the receiver is: ht s h 3 s h 1 s h 2 s ? >@ u = the jitter spectrum seen by the receiv er is the result of applying this system transfer function to the clock spectrum x(s) and is: ys xs h 3 s u h 1 s h 2 s ? >@ u = in order to generate time domain jitter numbers, an inverse fourier transform is performed on x(s)*h3(s) * [h1(s) - h2(s)]. pci express common clock architecture for pci express gen 1 , one transfer function is defined and the evaluation is performed over the ent ire spectrum: dc to nyquist (e.g for a 100mhz reference clock: 0hz ? 50mhz) and the jitter result is reported in peak-peak. pcie gen 1 magnitude of transfer function for pci express gen 2 , two transfer functions are defined with 2 evaluation ranges and the final jitter number is reported in rms. the two evaluation ranges for pci express gen 2 are 10khz ? 1.5mhz (low band) and 1.5mhz ? nyquist (high band). the plots show the individual transfer functions as well as the overall transfer function ht. pcie gen 2a magnitude of transfer function pcie gen 2b magnitude of transfer function for pci express gen 3 , one transfer function is defined and the evaluation is performed over the entire spectrum. the transfer function parameters are different from gen 1 and the jitter result is reported in rms. pcie gen 3 magnitude of transfer function for a more thorough overview of pci express jitter analysis methodology, please refer to idt application note pci express reference clock requirements.
femtoclock ? ng universal frequency translator 54 revision 1 08/07/15 8T49N241 data sheet power dissipation and thermal considerations the 8T49N241 is a multi-functional, high speed device that targets a wide variety of clock frequencies and applications. since this device is highly programmable with a broad range of features and functionality, the power consum ption will vary as these features and fun ctions are enabled. the 8T49N241 device is designed and characterized to operate withi n the ambie nt industrial temperature range of -40c to 85c. the ambient temperature represents the temperature around the device, not th e junction temperature. when using the device in extreme cases, such as maximum operating frequency and high ambient temperature, external air flow may be required in order to ensure a safe and relia ble junction temperature. extreme care must be taken to avoid exceeding 125c junction temperature. the power calculation examples below are generated using maximu m ambient temperature and supply voltage. for many applications, the power consumption will be much lower. please contact idt techni cal support for any concerns on calculating the power dissipation for your own specific configuration. power domains the 8T49N241 device has a number of separate power domains that can be independently enabled and disabled via register accesse s (all power supply pins must still be connected to a valid supply voltage). figure 16 below indicates the individual domains and the associated power pins. clk input & divider block (core v cc ) analog & digital pll (v cca & core v cc ) output divider / buffer q0 ( v cco0 ) output divider / buffer q1 (v cco1 ) output divider / buffer q2 (v cco2 ) output divider / buffer q3 ( v cco3 ) figure 16. 8T49N241 power domains power consumption calculation determining total power consumption involves several steps: 1. determine the power consumption using maximum curren t values for core and analog voltage supplies from table 8a and table 8b . 2. determine the nominal power consumption of ea ch enabled output path which consists of: a. a base amount of power that is independent of operating frequency, as shown in ta b l e 1 5 a through ta b l e 1 5 i (depending on the chosen output protocol). b. a variable amount of power that is re l ated to the output frequency. this can be determined by multiplying the output frequen cy by the fq_factor shown in ta bl e 1 5 a through table 15i . 3. all of the above totals are summed.
revision 1 08/07/15 55 femtoclock ? ng universal frequency translator 8T49N241 data sheet thermal considerations once the total power consumption has been determined, it is necessary to calculate the maximum operating junction temperature f or the device under the environmental conditions it will operate in. thermal con duction paths, air flow rate and ambient air temperature are factors that can affect this. the thermal conduction path refers to whether heat is to be conducted away via a heatsink, via airflow or via cond uction into the pcb through the device pads (including the epad). ther mal conduction data is provided for typical scenarios in table 14 below. please contact idt for assistance in calculatin g results under other scenarios. table 14. thermal resistance ? ja for 40-lead vfqfn, forced convection current consumption data and equations table 15a. 3.3v lvpecl ou tput calculation table table 15b. 3.3v hcsl output calculation table table 15c. 3.3v lvds output calculation table table 15d. 2.5v lvpecl output calculation table table 15e. 2.5v hcsl output calculation table table 15f. 2.5v lvds output calculation table table 15g. 3.3v lvcmos output calculation table table 15h. 2.5v lvcmos output calculation table ? ja by velocity meters per second 012 multi-layer pcb, jedec standard test boards 26.3c/w 23.2c/w 21.7c/w output fq_factor (ma/mhz) base_current (ma) q0 0.00660 32.9 q1 0.01088 44.4 q2 q3 output fq_facto r (ma/mhz) base_current (ma) q0 0.00647 33.5 q1 0.01050 44.7 q2 q3 output fq_factor (ma/mhz) base_current (ma) q0 0.00716 41.9 q1 0.01145 52.8 q2 q3 output fq_factor (ma/mhz) base_current (ma) q0 0.00483 27.6 q1 0.00865 38.3 q2 q3 output fq_factor (ma/mhz) base_current (ma) q0 0.00425 27.7 q1 0.00827 38.5 q2 q3 output fq_factor (ma/ mhz) base_current (ma) q0 0.00483 36.0 q1 0.00906 46.3 q2 q3 output base_current (ma) q0 31.3 q1 42.1 q2 q3 output base_current (ma) q0 25.8 q1 36.0 q2 q3
femtoclock ? ng universal frequency translator 56 revision 1 08/07/15 8T49N241 data sheet table 15i. 1.8v lvcmos output calculation table applying the values to the following equation will yield output current by frequency: qx current (ma) = fq_factor * frequency (mhz) + base_current where: qx current is the specific output current a ccording to output type and frequency fq_factor is used for calculating current increase due to output frequency base_current is the base current for each out put path independent of output frequency the second step is to multiply the power dissipated by the thermal impedance to determine the maximum power gradient, using the following equation: t j = t a + ( ? ja * pd total ) where: t j is the junction temperature (c) t a is the ambient temperature (c) ? ja is the thermal resistance value from table 14 , dependent on ambient airflow (c/w) pd total is the total power dissipation of the 8T49N241 under usage conditions, including power dissipated due to loading (w). note that the power dissipation per output pair due to loading is assumed to be 27.95mw for lvpecl outputs and 44.5mw for hcsl outputs. when selecting lvcmos outputs, power dissipation through the load will vary based on a variety of factors including termination type and trace length. for these examples, power dissipation through loading will be calculated using c pd (found in ta b l e 2 ) and output frequency: pd out = c pd * f out * v cco 2 where: pd out is the power dissipation of the output (w) c pd is the power dissipation capacitance (pf) f out is the output frequency of the selected output (mhz) v cco is the voltage supplied to the appropriate output (v) output base_current (ma) q0 22.8 q1 33.1 q2 q3
revision 1 08/07/15 57 femtoclock ? ng universal frequency translator 8T49N241 data sheet example calculations example 1. common customer configuration (3.3v core voltage) output output type frequency (mhz) v cco q0 lvpecl 125 3.3 q1 lvpecl 100 3.3 q2 lvpecl 50 3.3 q3 lvpecl 25 3.3 ? core supply current + control an d status supply current = i cc + i cccs = 54ma (max) ? analog supply current, i cca = 121ma (max) ? output supply current: q0 current = 125 * 0.00660 + 32.9 = 33.73ma q1 current = 100 * 0.01088 + 44.4 = 45.49ma q2 current = 50 * 0.01088 + 44.4 = 44.94ma q3 current = 25 * 0.01088 + 44.4 = 44.67ma ? total output supply current = 1 68.83ma (max) ? total device current = 54ma + 121ma + 168.83ma = 3 43.83ma ? total device power = 3.465v * 343.83ma = 11 91.37mw ? power dissipated through output loading: lvpecl = 27.95mw * 4 = 11 1.8mw lvds = already accounted for in device power hcsl = n/a lv c m o s = n / a ? total power = 1191.37mw + 111.8mw = 1303 .17mw or 1.3w with an ambient temperature of 85c and no airflo w, the junction temperature is: t j = 85c + 26.3c/w * 1.3w = 119.2c this is below the limit of 125c.
femtoclock ? ng universal frequency translator 58 revision 1 08/07/15 8T49N241 data sheet example 2. common customer configuration (2.5v core voltage) output output type frequency (mhz) v cco q0 lvpecl 156.25 2.5 q1 lvds 125 2.5 q2 hcsl 125 2.5 q3 lvcmos 25 2.5 ? core supply current + control an d status supply current = i cc + i cccs = 52ma (max) ? analog supply current, i cca = 118ma (max) ? output supply current: q0 current = 156.25 * 0.00483 + 27.6 = 28.35ma q1 current = 125 * 0.00906 + 46.3 = 47.43ma q2 current = 125 * 0.00827 + 38.5 = 39.53ma q3 current = 36.0ma ? total output supply current = 151.31 ma (max) ? total device current = 52ma + 118ma + 151.31ma = 3 21.31ma ? total device power = 2.625v * 321.31ma = 84 3.44mw ? power dissipated through output loading: lvpecl = 27.95mw * 1 = 27 .95mw lvds = already accounted for in device power hcsl = 45.5mw * 1 = 44 .5mw lvcmos = 16pf * 25mhz * (2.625v) 2 * 1 output pair = 2.76mw ? total power = 843.44mw + 27.95mw + 44.5mw + 2.76mw = 91 8.65mw or 0.919w with an ambient temperature of 85c and no airflo w, the junction temperature is: t j = 85c + 26.3c/w * 0.919w = 109.2c this is below the limit of 125c.
revision 1 08/07/15 59 femtoclock ? ng universal frequency translator 8T49N241 data sheet example 3. common customer configuration (2.5v core voltage) output output type frequency (mhz) v cco q0 lvpecl 250 2.5 q1 lvcmos 100 1.8 q2 lvcmos 50 1.8 q3 lvcmos 25 1.8 ? core supply current + control an d status supply current = i cc + i cccs = 52ma (max) ? analog supply current, i cca = 118ma (max) ? output supply current: q0 current = 250 * 0.00483 + 27.6 = 28.8ma q1 current = 33.1ma q2 current = 33.1ma q3 current = 33.1ma ? total output supply current = 28 .8ma (v cco = 2.5v), 99.3ma (v cco = 1.8v) ? total device current: 2.5v: 52ma + 118ma + 28.8ma = 198 .8ma 1.8v: 99.3ma ? total device power = 2.625v * 198.8ma + 1.89v * 99.3ma = 709 .5mw ? power dissipated through output loading: lvpecl = 27.95mw * 1 = 27 .95mw lvds = already accounted for in device power hcsl = n/a lvcmos = 6.87mw 13pf * 100mhz * (1.89v) 2 * 1 output pair = 4.64mw 13pf * 50mhz * (1.89v) 2 * 1 output pair = 2.32mw 13pf * 25mhz * (1.89v) 2 * 1 output pair = 1.16mw ? total power = 709.5mw + 27.95mw + 8.12mw = 7 45.57mw or 0.75w with an ambient temperature of 85c and no airflo w, the junction temperature is: t j = 85c + 26.3c/w * 0.75w = 104.7c this is below the limit of 125c.
femtoclock ? ng universal frequency translator 60 revision 1 08/07/15 8T49N241 data sheet reliability information table 16. ? ja vs. air flow table for a 40 lead vfqfn note: assumes 5x5 grid of thermal vias under epad area for thermal conduction. transistor count the transistor count for 8T49N241 is: 454,200 ? ja vs. air flow meters per second 012 multi-layer pcb, jedec standard test boards 26.3c/w 23.2c/w 21.7c/w
revision 1 08/07/15 61 femtoclock ? ng universal frequency translator 8T49N241 data sheet 40-lead vfqfn nl package outline www.idt.com d i t njo!1/31 njo!1/31
femtoclock ? ng universal frequency translator 62 revision 1 08/07/15 8T49N241 data sheet 40 lead vfqfn nl packag e outline, continued www.idt.com d i t
revision 1 08/07/15 63 femtoclock ? ng universal frequency translator 8T49N241 data sheet ordering information table 17. ordering information note: for the specific -ddd order codes, refer to femtoclock ng universal frequency tran slator ordering product information document. table 18. pin 1 orientation in tape and reel packaging part/order number marking package shipping packaging temperature 8T49N241-dddnlgi idt8T49N241-dddnlgi 40 lead vfqfn, lead-free tray -40 ? c to +85 ? c 8T49N241-dddnlgi8 idt8T49N241-dddnlgi 40 lead vfqfn, lead-free tape & reel -40 ? c to +85 ? c 8T49N241-dddnlgi# idt8T49N241-dddnlgi 40 lead vfqfn, lead-free tape & reel -40 ? c to +85 ? c part number suffix pin 1 orientation illustration nlgi8 quadrant 1 (eia-481-c) nlgi# quadrant 2 (eia-481-d) u s er direction of feed correct pin 1 orientation carrier tape top s ide (ro u nd s procket hole s ) u s er direction of feed correct pin 1 orientation carrier tape top s ide (ro u nd s procket hole s )
disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the right to modify the products and/or specif ications described herein at any time and at idt?s sole discretion. all information in this document, including descriptions of product features and performance, is subject to change without notice. performance spe cifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. the information co ntained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limi ted to, the suitab ility of idt?s products for any particular purpose, an implied war ranty of merchantability, or non-infringement of the intellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third pa rties. idt?s products are not intended for use in applications involvin g extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their o wn risk, absent an express, written agreement by idt. while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are implied. this produ ct is intended for use in normal commercial applications. any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recomme nded without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not authorize or warrant any idt product for use in life support devices o r critical medical instruments. integrated device technology, idt and the idt logo are registered trademarks of idt. product specification subject to change wi thout notice. other trademarks and service marks used herein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright ?2015 integrated device technology, inc. all rights reserved. corporate headquarters 6024 silver creek valley road san jose, ca 95138 usa sales 1-800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com tech support email: clocks@idt.com

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